Is VHDL still being used?

Thread Starter

Wolframore

Joined Jan 21, 2019
1,742
Is VHDL still being used? If so in what industries? I have a chance to learn it from an old guy through a class. It sounds fascinating but wondering how practical it is.
 

bogosort

Joined Sep 24, 2011
884
Is VHDL still being used? If so in what industries? I have a chance to learn it from an old guy through a class. It sounds fascinating but wondering how practical it is.
Definitely. We do our FPGA designs in VHDL (industrial machine monitoring). I learned VHDL in school, where it's still being taught. My understanding is that VHDL is more popular in the US, whereas Verilog is more popular in Europe.

The VHDL language itself is kind of clunky, but the real challenge is letting go of the top-down sequential flow mentality associated with compiled code and learning to think in terms of parallel hardware flow. Digilent sells relatively inexpensive and well-supported FPGA dev boards that can get you started, and the FPGA manufacturers offer free IDEs that of course support VHDL. It's fun; go for it!
 

Thread Starter

Wolframore

Joined Jan 21, 2019
1,742
Thanks @bogosort i was just looking at it and it reminds me a little of low level programming with Boolean logic. Wow it is amazing... it explains everything.

It takes so much to do things in it but gotta love how it addresses everything at the lowest level possible.
 
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Thread Starter

Wolframore

Joined Jan 21, 2019
1,742
Thank you @bertus I will play around and if I do end up taking the class I won’t be as lost. For me the true value is in understanding exactly at the hardware level what is going on when we code. It’s eye opening.
 

andrewmm

Joined Feb 25, 2011
222
VHDL very much in use,
and it is a lot more than Boolean,

Verlog and VHDL are both hardware description languages,
you can do things like A <= B * C; in both languages.

Typical verilog is debugged in simulators and other checking tools. VHDL is very very critical on its design, but a lot of the bugs are found at the design time, not down the line.

e.g. take the simple C <= A + B;

verilog and vhdl are both happy with this.
But if we define A and B are 8 bit numbers,
what happens if we define C as 8 bits.

VHDL, will tell you that you need 9 bits, and not compile.
Verilog will compile happily, and let you make silicon.
but did you mean to drop the top bit, or did you mean for C to be 9 bits but forgot.
so in VHDL you have to say what you want to do , in Veilog you could have made a mistake or not, hope your test bench finds it,

System Verilog, Sv as its called some times, has taken a lot of the points from VHDL,
but it has left all the old probems in , and relies upon you not to use the bad ays.

As for learning,

http://freerangefactory.org/pdf/df344hdh4h8kjfh3500ft2/free_range_vhdl.pdf
 
Definitely. We do our FPGA designs in VHDL (industrial machine monitoring). I learned VHDL in school, where it's still being taught. My understanding is that VHDL is more popular in the US, whereas Verilog is more popular in Europe.

The VHDL language itself is kind of clunky, but the real challenge is letting go of the top-down sequential flow mentality associated with compiled code and learning to think in terms of parallel hardware flow. Digilent sells relatively inexpensive and well-supported FPGA dev boards that can get you started, and the FPGA manufacturers offer free IDEs that of course support VHDL. It's fun; go for it!
Great answer thank you
 
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