Update:
- I tried to hook up the breadboard again, still to no success. Fried the Q1 2N7000 that controls the solenoid, due to it being on the whole time, from powering up the circuit, and for some reason (faulty cap?) managed to also ruin the 0.1uF C6 cap across header 2 and ground.
- Q2 seems to be holding the comparator output low all the time now, was worried i damaged something else but the 393 is OK, 4093 looks ok too.
- Main issue as above still persists, i get no timing action from the circuit, and the solenoid is energized the whole time..
- The reverse polarity protection works..

 

Hello. Below is the revised schematic.

Explanation:
- Top left with the SQ4401EY (I know, shouldnt use layout symbols but im new to EasyEDA), D1 and R1 is the reverse polarity protection.

- Top right with Q1, H3, LED2, R12, D3 and R11 is the solenoid control ( LED is to check for Q1 operation and solenoid status ).

- U2 with surrounding C1, LED1, R10, C2, L1 and D2 is the more efficient alternative to a 7805, due to the large voltage drop (24V to 5V). Values are picked according to the manufacturer datasheet for fixed voltage output.

- H2 with R2,R3,R4,U4,C3,R9 and R5 thru R8 is the comparator stage to prep the sensor output. R24,Q3,D6,R27,LED3 and C13 form the sensor output clamp (lockout) triggered by U5.

- C4, R13,C5,R14 along with U5 (CD4093) form a falling and rising edge detector. (C4 R13 for falling edge, C5 R14 for rising edge). Outputs of two gates are fed into the third, which is connected thru R23 to Q2 to trigger U3. C12 and R26 form another falling edge detector with the last remaining gate.

- Rest of the components (C11,R22,C7,C8,R21,D5,R15,D4,C6,U3,R16,C9,C10,SW1 and R17 thru R20) are support components for the 556, for delay and pulse length control.

How it works (at least in my head): Reverse polarity and solenoid control are self explanatory, as is pretty much the comparator stage. R5 thru R8 can be replaced by two DIP switches to change the lower and upper threshold voltage to change the sensors distance window.

R2 to R4 are jumper resistors.

LM2575 pin 5 is left unconnected, for the regulator to be enabled it needs to be grounded, otherwise if the pin sees voltage higher than 1,4V, it is disabled. Further room here to implement a delayed turn-on circuit, to delay the logic part a few seconds after the circuit is powered.

LM393s outputs are combined and pulled high with the R9 100k resistor, along with the 10uF capacitor. Idea is to slow down the rise of voltage as the comparator output goes high to act as some sort of a "filter".. depending on the size of the capacitor, quicker inputs in front of the sensor will be ignored, because the capacitor has no time to charge to a sufficient level to trigger the CD4093 input. (due to the schmitt trigger it should be 2/3 Vcc ?).

CD4093s first gate is used as a falling edge trigger, with the time constant of the output held high being set by C4 and R13, while the second gate is used as a rising edge trigger, with its time constant set by C5 and R14. The before mentioned "validation period" is set by the second gate, trigger for the timing part of the circuit is set by the first gate. Gate outputs are fed into the third gate inputs. If i understand it correctly, output of gate 1 is always low except when it is triggered. Output of gate two is always high except when triggered. If i elongate the time constant of gate 2 long enough, it should stay low until the first gate returns to low state, thus with the inputs combined into gate 3, gate 3 only goes high with the condition that both gate outputs coincide being low. Output of gate 3 drives Q2 to trigger the 556, for the initial timing delay, and output signal length control. Remaining gate is used as a second falling edge trigger, to facilitate lockout of the sensor output over Q3, however this part of the circuit is subject to change, since depending on the timing delay of the 556, lockout could time out before the 556 is timed out.

EDIT: different schematic is in. Change is to gate 4 trigger location, now being triggered by the low edge signal provided by the first timing stage of the 556. Do not think this solves the issue ...

 

Hello.

Nevermind the last part of the previous post, had a major case of fart for brains and completely went over the fact that the nand gate thruth table goes completely opposite of what i need it to do. Unless i substitute Q2 with a PNP transistor. Or use the last gate to invert output of gate 2..

 

Here is the completed circuit after some breadboard testing.


Some comments:
- Problem with the CD4093 was that i burnt out the first one (managed to burn out gate #4), so i was extra careful with the new one, my guess is i shorted the leads when probing. Problem with the logic was that i needed to invert output of gate 2 so, and delay its decay to 0 with C12 for long enough that it is picked up as logic state "1" on the gate #4 input, coupled with the output of gate#1, so that it gives a 0 on gate #4 output. Output hooked up to a two NPN transistors as a NOT gate, used what i had laying around. (Two BC637s).
- Input lockout is done by activating the lockout with 556 output A, and delaying it by further ~10s via C13 R27 and D7. D6 is to keep C13 from discharging thru the LED5 and R26 (used to visually represent delay time).

Thank you all who provided insight, i am still open to suggestions on how to improve this circuit.

EDIT: Pin 5 of LM2575 will be grounded for now. Missing connection from pin 4 of CD4093 goes to pins 13 and 12.