.....or......

always @(posedge  clk )
        begin
           if (ld==1)
           begin
                q0 <= d0;
                q2 <= d2;
                q1 <= d1;
           end
       end

See how each one happens at the positive edge of clk and when ld is 1?

 

Hell no. What i meant was:

module register(
input {3:0] D,
input ld,
input clk,
output [3:0] Q);

always @(posedge clk)
        begin
           if (ld==1) Q <= D;
        end
endmodule

and then for example:

module core_v(clk, ld1, ld2, ld3, D, Q);
        input  [3:0] D;
        input clk;
        input ld1, ld2, ld3;
        output [3:0] Q;
        wire  [3:0] X,Y;

  register Reg1(D, ld1, clk, X);
  register Reg2(X, ld2, clk, Y);
  register Reg31(Y, ld3, clk, Q);
endmodule

 

first you make your component "register", and then use three pieces of that component in core_v. Are we getting somewhere?

 

You can use that component in any file in your project. Just keep every module in its own file to make the project easy to understand.

 

Well, forty something posts later...
Read again posts #30, #32 and #35 and do what I asked about a century ago. And I mean everything, that means the result will be a zip file with a tested and working project.

 

. And I mean everything, that means the result will be a zip file with a tested and working project.

are you getting zip file ?

 

Yes, that is a zip file. Next time put the quartus project inside.

 

That is a word file, I asked for the whole quartus project.

 

I see a few problems with your code. Yes it does compile without errors, but thera are 64 warnings that need to be corrected, and quite a few errors that are not errors in syntax, but errors in the logic of the design.
Second thing, you have five different allways block that have nothing in common. I can barely understand what the code is supposed to do, there is just too much going on in one module. It is nice that you are trying to do something more, but clearly you dont have the skills to do it correctly which just adds to the overall clutter.
Which is why I wanted you to do just the ALU and three registers, so that you learn how the structure of your code should look like and how to test your design. So far you are ingoring all of my requests which is getting rather annoying.
You need to make your code from small pieces, so that you can test each piece individually and then connect the pieces to larger groups.

 

I see a few problems with your code. Yes it does compile without errors, but thera are 64 warnings that need to be corrected,

can I use this method ?

and quite a few errors that are not errors in syntax, but errors in the logic of the design.

I knew and I did mention in my post

Which is why I wanted you to do just the ALU and three registers, so that you learn how the structure of your code should look like and how to test your design. So far you are ingoring all of my requests which is getting rather annoying.

I am really sorry
ok look at this file for fig 2.13

 

i got a lot of work today, so maybe later in the evening ill have time for this.

 

Ok just checked that last zip. All there is is a top level file mcu.v with nothing else. Where is the code for core_v? Where is the rest of the components that you use there?
The code you posted does nothing. I am pretty sure I asked for a specific set of parts connected together in a specific way, and also asked you to make a test which shows that the result works as it should. You did nothing of what I asked you for.
So either you do what I ask, and exactly as I ask, or there is no reason for me go on with this. I gave you specific assignement to do so please do it. If you dont understand anything then ask, I have no problem with explaining any questions you might have. But if you dont ask anything and still do something completely different, then I am not going help you anymore.

 

also asked you to make a test which shows that the result works as it should

which type of test are you talking? did you mean RTL view or Time graph ?
I am uploading two zip file
I have made first file according to post #35
In my first zip I have done following work
//top module
//input declaration
//output declaration
//interconnect wires
//component that used in top module

I have made second file according #59
In second zip file I use one file for all registers then I have used all in top module
ok just check out that files tell me

 

Ok the code inside new folder 6 seems like it is going the right way. Now look again at fig 2.13 and make code that does what it is on the picture, nothing less, nothing more.
When you are done, make another file that will instantiate core_v and put values on the inputs and show a time graph of the outputs.

 

Ok the code inside new folder 6 seems like it is going the right way.

ok thank you very much .

Now look again at fig 2.13 and make code that does what it is on the picture, nothing less, nothing more.

I don't understand whats wrong with this code. If you will tell me my mistakes I think its very good for me. but ok I am trying to make batter

 

Oops, I missed even more serious errors yesterday. In the new folder 6, you have seven instances of register, and no instance of alu.
You should have three instances of register, with names accumulator, tempreg and tempacc, and one instance of alu and lets call it alu1.

 

ok look this code I am trying my best
look this and tell me whats wrong with this code

 

You still have no clue what the things that you write do.

module core_v(clk, ld1, ld2, ld3, D, z,ld4,ld5,ld6);
input  [3:0] D;
  input clk;
  input ld1, ld2, ld3,ld4,ld5,ld6;
  output [3:0] z;
  wire s1,s2,s3,s4,s5,s6,z;

  register acc (s3,ld4,clk,s4);
  register tempacc(s4,ld5,clk,a);
  register tempreg (s3,ld6,clk,b);
  alu alu1 (a,b,z);
endmodule


module register(D,ld,clk,Q);
input D;
input ld;
input clk;
output  Q;
reg[3:0] Q;
always @(posedge clk)
  begin
  if (ld==1) Q <= D;
  end
endmodule

module alu (a,b,sel,z);
input [8:0]a,b;  // input for alu
  input [3:0]sel;  // select input
  output [7:0]z;
reg [7:0]z;
always@(sel,a,b) 
begin
case(sel)
4'b0000: z=a+b;  // do AND logic
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule

Is the way the structure should look like. But for the last time, put each module in its own file - module register will be in file register.v and module alu will be in file alu.v. I was hoping that when you do that you will start to see how the components are used, but you keep ignoring that.

After you do that: correct the definitions of the internals according to the fact that register is 8 bit wide and alu is 8 bit wide.
And of course the inputs, outputs and wires in corev_v are most likely incorrect.

 

can you see which parts I deleted? All the deleted modules were not used.

 

why? and why didnt you use it in the corev_v ?