input and output signal for microcontroller

Thread Starter

vead

Joined Nov 24, 2011
629
I am willing to go through this with you.
thank you very much

I am using quartus II
cyclone III

Write code for the accumulator:
Inputs:
4bit data Din
LD - load enable signal
clock
Outputs:
4bit data Dout

Code:
module acc(clk, ld, d, q);
        input        clk, ld;
        input  [3:0] d;
        output [3:0] q;
        reg    [3:0] tmp;
        always @(posedge clk or posedge ld)
        begin
           if (ld)
              tmp <= 4'b1111;
           else
              tmp <= tmp + d;
        end
           assign q = tmp;
        endmodule
simulation reports

Code:
Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 227 megabytes
    Info: Processing ended: Sat Sep 20 11:08:15 2014
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01
 

kubeek

Joined Sep 20, 2005
5,794
Cool, looks like we are getting somewhere. However I am not sure why you have these two lines:
if (ld)tmp <= 4'b1111;
else tmp <= tmp + d;
I dont really think this does what I asked, but I guess it si most likely an error in translation and understanding what is meant by accumulator - from the descritpion it should have been just a latch with load enable input.

I imagined it would look more like this:
Code:
module acc(clk, ld, d, q);
        input clk, ld, [3:0] d;
        output reg [3:0] q;
        always @(posedge clk)
        begin
           if (ld==1) q <= d;
        endmodule
 

kubeek

Joined Sep 20, 2005
5,794
I guess the boxes like alu should be inside the microcontroller, not outside. And the wires should be between those boxes and have names.
 

kubeek

Joined Sep 20, 2005
5,794
Internet is full of diagrams that you can use. Also, if you must draw them it might be easier to do on paper than in software.
Also, when I said implement the figure 2.13, what I mean is the following:
top level file, lets call it core.v, and in it:
bidirectional data bus
three instances of the register I wrote in post #29
your ALU
one instance of register, with bidirectional data path, load/!store input, enable input and clock input.
All connected together such that it works like shown in fig 2.13.
core.v will have as i/o the clkoc, data bus, and all the control signals for the above blocks. Then you should test it. Try setting the control signals such that you can load the accumulator, then the temp acc and temp reg, do some operation with those and then store the result back in the accumulator and the register.
 

kubeek

Joined Sep 20, 2005
5,794
I dont understand, why would you want to re-draw such a useless digram? You have no idea what the parts do, or why they are done the way they are, and yet you still waste youre time trying to draw your own. Please use your time on doing something that actually gets you somewhere.
 

kubeek

Joined Sep 20, 2005
5,794
good, after you test that it works, you could zip your project file and upload it. Im going to download quartus ii web edition so that I can load your project easily.
 

Thread Starter

vead

Joined Nov 24, 2011
629
sir,
I compiled code but I am getting one error
look at this code
Code:
module core_v.v(clk,ld, r0_i,r1_i,r2_i,r0_o,r1_o,r2_o,acc_i,f);

input clk;
input ld;

input r0_i,r1_i,r2_i;
output r0_o,r1_o,r2_o;

input acc_in;
output f;

input[3:0]r0_i;
input[3:0]r1_i;
input[3:0]r2_i;

output[3:0]r0_o;
output[3:0]r1_o;
output[3:0]r2_o;

input [3:0]acc_in;

output [3:0]f;

// add r0

//add r0
module core_vr0 (clk, ld, d0, q0);
        input clk, ld, [3:0] d0;
        output reg [3:0] q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
        endmodule

// add r1
        module core_vr1 (clk, ld, d1, q1);
        input clk, ld, [3:0] d1;
        output reg [3:0] q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
        endmodule

//add r2
module core_vr2_i (clk, ld, d2, q2);
        input clk, ld, [3:0] d2;
        output reg [3:0] q2;
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
          
        endmodule

// add acc
module core_vacc(clk, ld, d, q);
        input clk, ld, [3:0] d;
        output reg [3:0] q;
        always @(posedge clk)
        begin
           if (ld==1) q <= d;
        endmodule

//add temacc       
module core_tempacc(clk, ld, d2, q2);
        input clk, ld, [3:0] d2;
        output reg [3:0] q2;
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
        endmodule

// add accreg       
module core_v accreg(clk, ld, d3, q3);
        input clk, ld, [3:0] d3;
        output reg [3:0] q3;
        always @(posedge clk)
        begin
           if (ld==1) q3 <= d3;
        endmodule
       
// add alu
module alu (q2,q3,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;
endmodule

endmodule
 

kubeek

Joined Sep 20, 2005
5,794
thats too easy.. The compiler is complainig about a "." (dot) on line 3. Can you guess which dot it is? Try to be a bit more independent please.
 

Thread Starter

vead

Joined Nov 24, 2011
629
now please look at this code I made with no error
Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 227 megabytes
Info: Processing ended: Tue Sep 23 05:55:34 2014
Info: Elapsed time: 00:00:06
Info: Total CPU time (on all processors): 00:00:04

Code:
module core_v(clk,ld, );

input clk;
input ld;



//add r0
core_v core_vr0 ( d0, q0);
        input  [3:0] d0;
        output q0;
         reg [3:0] q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
     

// add r1
        core_v core_vr1 ( d1, q1);
        input  d1;
        output q1;
         reg [3:0] q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
        end

//add r2
core_v core_vr2_i ( d2, q2);
        input  d2;
        output  q2;
        reg [3:0] q2;
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
       
        end

// add acc
core_v core_vacc( d, q);
        input  d;
        output q;
         reg [3:0] q;
        always @(posedge clk)
        begin
           if (ld==1) q <= d;
        end

//add temacc    
core_v core_tempacc(clk, ld, d3, q3);
        input  d3;
        output q3;
         reg [3:0] q3;
        always @(posedge clk)
        begin
           if (ld==1) q3 <= d3;
        end

// add accreg    
core_v core_tempreg(clk, ld, d4, q4);
        input  d4;
        output q4;
        reg [3:0] q4;
        always @(posedge clk)
        begin
           if (ld==1) q4 <= d4;
        end
     
//add alu   
core_v core_alu (z,a,b,sel);
input [8:0]a,b;
input [3:0]sel;
output [8:0]z;
reg [8:0]z;
always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule
 
Last edited:

kubeek

Joined Sep 20, 2005
5,794
now please look at this code I made with no error
Interestingly enough, when I paste that code into xilinx ise, I get 23 errors. Please look back at post #22 and carefuly look at how the modules are used and defined - each module definition should be in its own file.
 

kubeek

Joined Sep 20, 2005
5,794
well you could do what I said before, put each module definition into its own file. What you posted may compile without errors (which I doubt, but we´ll see later), but still it is written wrong and I bet it will not work as intended. Read once again how the definition of a module should look like, and how to use the instances.
 

kubeek

Joined Sep 20, 2005
5,794
Ok, this is what I get: (had to rename core_v to test1 beacause of the way quartus needs the names)
Code:
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
    Info: Processing started: Mon Sep 22 18:06:04 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test1 -c test1
Warning (20028): Parallel compilation is not licensed and has been disabled
Warning (10238): Verilog Module Declaration warning at test1.v(1): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "test1"
Info (12021): Found 1 design units, including 1 entities, in source file test1.v
    Info (12023): Found entity 1: test1
Error (10206): Verilog HDL Module Declaration error at test1.v(10): top module port "d0" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(12): data type declaration for "q0" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(11): see declaration for object "q0"
Error (10206): Verilog HDL Module Declaration error at test1.v(11): top module port "q0" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(21): top module port "d1" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(23): data type declaration for "q1" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(22): see declaration for object "q1"
Error (10206): Verilog HDL Module Declaration error at test1.v(22): top module port "q1" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(31): top module port "d2" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(33): data type declaration for "q2" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(32): see declaration for object "q2"
Error (10206): Verilog HDL Module Declaration error at test1.v(32): top module port "q2" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(42): top module port "d" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(44): data type declaration for "q" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(43): see declaration for object "q"
Error (10206): Verilog HDL Module Declaration error at test1.v(43): top module port "q" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(52): top module port "d3" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(54): data type declaration for "q3" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(53): see declaration for object "q3"
Error (10206): Verilog HDL Module Declaration error at test1.v(53): top module port "q3" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(62): top module port "d4" is not found in the port list
Warning (10227): Verilog HDL Port Declaration warning at test1.v(64): data type declaration for "q4" declares packed dimensions but the port declaration declaration does not
Info (10499): HDL info at test1.v(63): see declaration for object "q4"
Error (10206): Verilog HDL Module Declaration error at test1.v(63): top module port "q4" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(72): top module port "a" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(72): top module port "b" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(73): top module port "sel" is not found in the port list
Error (10206): Verilog HDL Module Declaration error at test1.v(74): top module port "z" is not found in the port list
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 16 errors, 8 warnings
    Error: Peak virtual memory: 558 megabytes
    Error: Processing ended: Mon Sep 22 18:06:06 2014
    Error: Elapsed time: 00:00:02
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 18 errors, 8 warnings
 

kubeek

Joined Sep 20, 2005
5,794
First need to define what a port is and how it should behave. When you know that, you will know how to write it in code.
 

Thread Starter

vead

Joined Nov 24, 2011
629
hello ,

when i compile code I am getting following 3 error
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 5 warnings
line if (ld==1) q4 <= d4;

Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type
Code:
module core_v(clk,ld,d0, q0,d1,d2,q1,q2,a,b,z,sel,d,q,d3,q3,d4,q4 );

input clk;
input ld;
reg [3:0] q0;
reg [3:0] q1;
reg [3:0] q2;
reg [3:0] z;

 

//add r0
core_v core_vr0 ( d0, q0);
        input  [3:0] d0;
        output q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
    

// add r1
        core_v core_vr1 ( d1, q1);
        input  d1;
        output q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
        end

//add r2
core_v core_vr2_i ( d2, q2);
        input  d2;
        output  q2;
       
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
      
        end

// add acc
core_v core_vacc( d, q);
        input  d;
        output q;
         reg [3:0] q;
        always @(posedge clk)
        begin
           if (ld==1) q <= d;
        end

//add temacc   
core_v core_tempacc(d3,q3 );
        input  d3;
        output q3;
        always @(posedge clk)
        begin
         if (ld==1) q <= d;
         end
     

// add accreg   
core_v core_tempreg(clk, ld, d4, q4);
        input  d4;
        output q4;
       
        always @(posedge clk)
        begin
           if (ld==1) q4 <= d4;
        end
    
//add alu  
core_v core_alu (z,a,b,sel);
input a, b;
input sel;
output z;

always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule
 
Top