thank you very muchI am willing to go through this with you.
I am using quartus II
cyclone III
Write code for the accumulator:
Inputs:
4bit data Din
LD - load enable signal
clock
Outputs:
4bit data Dout
Code:
module acc(clk, ld, d, q);
input clk, ld;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge ld)
begin
if (ld)
tmp <= 4'b1111;
else
tmp <= tmp + d;
end
assign q = tmp;
endmodule
Code:
Info: Quartus II Analyze Current File was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 227 megabytes
Info: Processing ended: Sat Sep 20 11:08:15 2014
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01