I want to write input and output for microcontroller in verilog langugae

I have done some work

Microcontroller has following function

· ALU

· Decoder

· Port

· Counter

· Interrupt

· Accumulator

· Stack pointer

· Data pointer

· Special function register

· Serial communication

· Internal rom

· External rom

· Internal ram

· External Ram


Verilog code

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out, a,b, s0,s1,s2, a0,a1,a2,d0,d1,d2,d3,d4,d5,d6.....etc )

Rst= reset input
Clk=  clock input
En= enable input

Port
P_in=port input
P_out= port output

Timer
T_in = timer input
T_out = timer output

Interrupt
i_in= input for interrupt
i_out,= output for interrupt

ALU
A=input
B=input
So=input
S1=input
S2=input
F=output

Decoder
opcode_in
opcode_out

ram
wr
wd

ram
read
write
enable

Can anyone tell me how to write input and output for microcontroller in verilog langugae ?

 

Any Verilog tutorial will show you how to define inputs and outputs...

 

If you are still attempting a soft processor (e.g. a microcontroller implemented on a FPGA, or some other PLD), then the microcontroller is comprised of many smaller modules (e.g. I/O direction control register, ALU, etc.).

The soft microcontroller is arranged in much the same way as many other Verilog components are: they have prescribed inputs and outputs as part of the architecture - you just need to route signals where they need to then go.

Make a top level, Verilog module called microcontroller.v and put everything the controller requires inside (instantiate each instance) and connect the various components together as they should be.

 

This is were a tutorial comes in handy.

See here.

You first instantiate a module, then start adding the requisite components. Someone that learned Verilog should be able to do this (specific syntax notwithstanding, but the general idea should be there).

module microcontroller (
clk,
rst_0,
PA1,
//etc...
);

//Input declaration
input clk;
input rst_0;
//etc.

//Output declaration
//define outputs

//Interconnect signals
wire GlobalOE_0;
wire PA[7:0];
wire PB[7:0];
wire PA_control;
wire PB_control

//I/O controller
IOController ioCntrl(
PA_control,
PB_control,
//etc.
);

//Add I/O Port A
IOPort PA(
PA[7:0],
PA_control,
GlobalOE_0
);

//Add I/O Port B
IOPort PB(
PB[7:0],
PB_control,
GlobalOE_0
);

//etc.

End module;

Keep in mind I typically use VHDL, so the syntax may be off...

 

This is were a tutorial comes in handy.

See here.

You first instantiate a module, then start adding the requisite components. Someone that learned Verilog should be able to do this (specific syntax notwithstanding, but the general idea should be there)

Keep in mind I typically use VHDL, so the syntax may be off...

it helped me a lot thank for giving general idea

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
Rst= reset input
Clk=  clock input
En= enable input
Port
P_in=port input
P_out= port output

Timer
T_in = timer input
T_out = timer output

Interrupt
i_in= input for interrupt
i_out,= output for interrupt

ram
wr
wd

ram
read
write
enable

Module alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case
End module



Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
Endmodule

first I have define input output example ALU, DECODER, PORT ....etc
then I made code for inner part example ALU, decoder
how to route alu with decoder . (I am asking for handy code

 

How did you design your decoder to interact with the ALU? Follow whatever logic diagram you made when designing the controller.

I'm confused as to why your are asking us about your design. You are the one making this controller.

If you made the pieces without being sure of how to connect them, you need to spend some of your time figuring it out. Simply defining things and attempting to cobble them together later is a good way to waste a lot of time. Design with a plan.

 

How did you design your decoder to interact with the ALU

decoder connect with address bus , data bus ,control bus

I'm confused as to why your are asking us about your design

I have spend lot of time. I am not designing for company.
i am student I don't care what I will make. I just want to learn way ,
I know designing controller is not easy . It need more reading and practice
I did search more but I could not find how to add alu , decoder , program counter and other
so I just wrote code for alu, and decoder
so I did ask here how to connect ALU with decoder

 

In a few minutes of searching, I've found a great deal of information showing what to do.

See the following:

• http://www.altera.com/education/univ/materials/digital_logic/labs/unv-labs.html
• • ftp://ftp.altera.com/up/pub/Altera_Material/12.0/Laboratory_Exercises/Digital_Logic/DE2-115/verilog/lab9_Verilog.pdf
• http://www.slideshare.net/n380/elementary-processor-tutorial

I'd recommend you stop getting ahead of yourself and latching on to the words you see and learn the design principles from the ground up, otherwise, you'll have only the vocabulary with none of the understanding.

 

sorry but still I am confused I don't see any statement that show that my controller is connected with ALU, decoder

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
Rst= reset input
Clk=  clock input
En= enable input
Port
P_in=port input
P_out= port output

Timer
T_in = timer input
T_out = timer output

Interrupt
i_in= input for interrupt
i_out,= output for interrupt

ram
wr
wd

ram
read
write
enable

Module alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case
End module



Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
Endmodule

how to show in code that microcontroller is connected with some component(ALU, decoder, program counter ..) and they are wired together

 

sorry but still I am confused I don't see any statement that show that my controller is connected with ALU, decoder

Why does it need to be connected? What makes you think it should be connected? What purpose would it serve?

 

how to show in verilog code that alu , decoder ,counter are connected together?

See my previous post...

This is were a tutorial comes in handy.

See here.

You first instantiate a module, then start adding the requisite components. Someone that learned Verilog should be able to do this (specific syntax notwithstanding, but the general idea should be there).

module microcontroller (
clk,
rst_0,
PA1,
//etc...
);

//Input declaration
input clk;
input rst_0;
//etc.

//Output declaration
//define outputs

//Interconnect signals
wire GlobalOE_0;
wire PA[7:0];
wire PB[7:0];
wire PA_control;
wire PB_control;

//I/O controller
IOController ioCntrl(
PA_control,
PB_control,
//etc.
);

//Add I/O Port A
IOPort PA(
PA[7:0],
PA_control,
GlobalOE_0
);

//Add I/O Port B
IOPort PB(
PB[7:0],
PB_control,
GlobalOE_0
);

//etc.

End module;

[...]

Note the portion labeled "Interconnect Signals" - this is where the signal called "PA_control" (declared as a wire) is instantiated. By following all of the places this signal name is used, we know that IOPort PA is connected to the IOController.

can you tell me the statement that is use to route one component to other?

You connect modules at the same hierarchical levels with wires. Modules lower in the hierarchy are connected by modifying/connecting to inputs & outputs from the parent module.

 

ok I am trying ,look at below

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);
//Input, output  declaration
Rst= reset input
Clk=  clock input
En= enable input
Port
P_in=port input
P_out= port output

Timer
T_in = timer input
T_out = timer output

Interrupt
i_in= input for interrupt
i_out,= output for interrupt

ram
wr
wd

ram
read
write
enable

//Interconnect signals
wire alu [3:0]
wire decoder [7:0]

// add alu
Mcu_alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;


//Add decoder

Mcu_decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
Endmodule

 

You should use a much shorter and simpler example to see how it should be done.

module HalfAdder (A,B,S,C)
  input A,B;
  output S,C;

  xor sum (S,A,C);
  and Carry(C,A,B);
endmodule

module FullAdder(A,B,Cin,S,Cout);
  input A, B, Cin;
  output S, Cout;
  wire S1, C1, C2;

  HalfAdder HA1(A, B, S1, C1);
  HalfAdder HA2(S1, Cin, S, Cout);
  or Carry (Cout, C1, C2);
endmodule

Here you can see, that in the module FullAdder you are using two instances of the component half adder, and zou can see how they are connected to the module's inputs and outputs and how they are connected together.

You should keep each module in separate file, it makes debugging much easier.

Now, try and make a 4-bit adder using four instances of FullAdder, and connect each Cout to the next Cin.

I took these examples from here (part 3) http://3bdalladalleh.wordpress.com/...ith-verilog-hdl-tutorial-part-1-introduction/ which seems like a nice tutorial.

 

look this work

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);

//Input, output  declaration
Rst= reset input
Clk=  clock input
En= enable input
Port
P_in=port input
P_out= port output
Timer
T_in = timer input
T_out = timer output
Interrupt
i_in= input for interrupt
i_out,= output for interrupt
ram
wr
wd
ram
read
write
enable

//Interconnect signals
wire alu [3:0]
wire decoder [7:0]
reg counter [3:0]

// add alu
Mcu_alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;

//Add decoder
Mcu_decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000:( d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100:( d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101:( d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase

//add counter
module up_counter(current state, next state ,clk)
input current state ;
input clk;
output next state;
reg 3:0
always @ (posedge clk);
begin
next state <= current state +1 ;
end
endmodule

 

nope that doesnt work. Keep the modules separate, make the definition of ALU in one file, and than use it in the MCU. Look at my example.

 

You are missing endmodule after each module. I edited your code to reflect that. See how ALU1 and CTR1 are connected together.
edit: code tag doesnt work very well with bold letters etc.

Module mcu (clk, rst, en, p_in, p_out, t_in, t_out, i_in,i_out, rx_in, tx_out ,a0,a1,a2,d0,d1,d2,d3,d4,d5,d6,d7,a,b,s0,s1,s2,f,........etc);

//Input, output declaration
Rst= reset input
Clk= clock input
En= enable input
Port
P_in=port input
P_out= port output
Timer
T_in = timer input
T_out = timer output
Interrupt
i_in= input for interrupt
i_out,= output for interrupt
ram
wr
wd
ram
read
write
enable

//Interconnect signals
wire alu [3:0]
wire decoder [7:0]
reg counter [3:0]

//here you should have the insantiation of the modules you wish to use
//for example:
alu ALU1 (clk, rst, wire1, wire2 ...);
up_counter CTR1 (wire1, wire2, clk)
endmodule;



// add alu
module alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;
endmodule


//Add decoder
Module decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000: (d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100: (d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101: (d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
endmodule

//add counter
module up_counter(current state, next state ,clk)
input current state ;
input clk;
output next state;
reg 3:0
always @ (posedge clk);
begin
next state <= current state +1 ;
end
endmodule

 

look at this code there is another way to connect one component to other
Is it correct way to connect with another ,?

module mcu_8051 (rst, clk ,

// interrupt interface
                int0_i,
                int1_i,
// port interface
  `ifdef mcu_port 
        `ifdef mcu_port0
                p0_i,
                p0_o,
        `endif
        `ifdef mcu_port1
                p1_i,
                p1_o,
        `endif
        `ifdef mcu_port2
                p2_i,
                p2_o,
        `endif
        `ifdef mcu_port3
                p3_i,
                p3_o,
        `endif
  `endif
// serial interface
        `ifdef mcu_uart
                rxd_i, txd_o,
        `endif
// counter interface
        `ifdef mcu_tc01
                t0_i, t1_i,
        `endif
        `ifdef OC8051_tc2
                t2_i, t2ex_i,
        `endif

what is mean by ifdef and endif ?

 

Vead, please actually learn this material. Look at a tutorial, understand the concepts, then attempt to apply them to your current design.

Finding code that someone else wrote won't help you if you don't understand the concepts.

Before you ask a question, try Google. Searching for "ifdef Verilog" in Google gives plenty of examples and explanations that it is a compiler directive.

Some up front effort on your part would make this process easier...

 

hello experts

I have done little homework
designing controller is not easy so I have divided my homework
first I have developed algorithem

(algorithm )

Design for microcontroller

Verilog code

What is Input for microcontroller

What is Output for microcontroller

// I write module for microcontroller

//input deceleration

// output deceleration

// interconnect signal

// I make inner part (alu decoder pc timer….)

// I route all inner part

Endmodule

I have applied this algorithm in following code

// module for microcontroller 
module mcu_8051(clk,rst,p0_in,p1_in,p2_in,p3_in,p0_out,p1_out,p2_out,p3_out,rx_in  tx_out ,into,int1,to_in,t1_in,wr,wd , op_in, op_out, scr1,scr2,scr3

// input and output declaration

// port         
p0_in, p1_in, p2_in, p3_in;        // port input
p0_out,p1_out,p2_out,p3_out  // port output

// clock input
Clk;                         // clock input

//rest input
Rst                         // reset in input

//Uart
rx_in                         // receive
tx_out               // transmit

//timer
to_in,                                            //timer t0 input
t1_in                                             // timer t1 input

// interrupt
int0,                                             // interrupt 0 input       
int1                                             // interrupt 1 input         

//alu

src1,       // alu source 1
src2,       // alu sources 2
src3,       // alu sources 3

//decoder
Opcode_in    // operation code input
Opcode_output // operation code output

// program memory
Rd_in       //  read input 
adr_o     // input
data_out   // data ouput

// data memory
Rd_in   //  read input
Wd_in     // write in
Adr_in     // address input
Data _in    // data input
Data_out    // data output

Interconnect signal
             input[ 7:0] p0_in
             inpu[7:0]p1_in
             input [7:0] p2_in

input [7:0]p3_in
output [7:0] p0_out,
output [7:0] p1_out,
output [7:0] p2_out,
output [7:0] p3_out,
 
wire [7:0]opcode_in
wire [7:0]opcode_out
wire [7:0] acc
wire [7:0] pc
wire [7:0] data_in
wire [7:0] data_out
wire [7:0] scr1
wire [7:0] scr2
wire [7:0] scr3
wire [7:0] opcode_in
wire [15:0]pc ;

// add port p0
Module mcu_port0(input, output)
Input ..;
Output…;
Endmodule

// add port p1
Module mcu_port1(input, output)
Input ..;
Output…;
Endmodule

// add port p2
Module mcu_port2(input, output)
Input ..;
Output…;
Endmodule

// add port p3
Module mcu_port3(input, output)
Input ..;
Output…;
Endmodule


// add alu
module mcu_ alu (a,b,s0,s1,s2 f);
Input a,b,s0,s1,s2;
Output f;
Reg [3:0];
Always @(s0,s1,s2);
Begian
Case (s0,s1,s2);
3b’000 :f=(a&b);
3b’001:f= (a|b);
3b’010 :f= ~(a&b);
3b’011 :f= ~ (a|b);
3b’100:f=(a^b);
3b’101: f=(a*b);
3b’110: f=(a+b);
3b’111:f=(a-b );
End case;
endmodule

//Add decoder
Module mcu_ decoder (a2,a1,a0, d7,d6,d5,d4,d3,d2,d1,d0);
Input a2,a1,a0;
Output d7,d6,d5,d4,d3,d2,d1,d0;
Wire [7:0];
Always @(a2,a1,a0);
Begin
Case (a2,a1,a0);
4’b000: (d7,d6,d5,d4,d3,d2,d1,d0)=00000001;
4’001: (d7,d6,d5,d4,d3,d2,d1,d0)=00000010;
4’b010: (d7,d6,d5,d4,d3,d2,d1,d0)=00000100;
4’b011: (d7,d6,d5,d4,d3,d2,d1,d0)=00001000;
4’b100: (d7,d6,d5,d4,d3,d2,d1,d0)=00010000;
4’b101: (d7,d6,d5,d4,d3,d2,d1,d0)=00100000;
4’b110: (d7,d6,d5,d4,d3,d2,d1,d0)=01000000;
4’b111: (d7,d6,d5,d4,d3,d2,d1,d0)=10000000;
Endcase
endmodule

//add counter
module mcu _counter(current state, next state ,clk)
input current state ;
input clk;
output next state;
reg 3:0
always @ (posedge clk);
begin
next state <= current state +1 ;
end
endmodule

‘’’’’’’’
;;;;;;;;;;;;;
;;;;;;;;;;;;;;
End other component
endmodule

 

I dont think you need alogrithm and start writing up silly lists of features, when you have no idea what is their purpose and how will they fit with the rest. You are building the roof before you even started building the basement.
Start with simple things, and connect them together as you go along.
Like I said somewhere eariler, make the basic components first. You have the ALU sort of ready, forget about the controller for now. You should decide what kind of architecture you want, and I suggest you go with a single accumulator and a load/store architecture. I am willing to go through this with you, but you need to do what I say.
Write code for the accumulator:
Inputs:
4bit data Din
LD - load enable signal
clock
Outputs:
4bit data Dout

make it such that Dout is allways outputting what is stored inside the accumulator. On rising edge of clock and when LD==1, the old value in the accumulator gets replaced by Din.
Write the code, and verify in simulator that it does what it should.