input and output signal for microcontroller

vead · Sep 23, 2014

hello ,

when i compile code I am getting following 3 error
Error: Quartus II Full Compilation was unsuccessful. 3 errors, 5 warnings
line if (ld==1) q4 <= d4;

Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type

Code:

module core_v(clk,ld,d0, q0,d1,d2,q1,q2,a,b,z,sel,d,q,d3,q3,d4,q4 );

input clk;
input ld;
reg [3:0] q0;
reg [3:0] q1;
reg [3:0] q2;
reg [3:0] z;

 

//add r0
core_v core_vr0 ( d0, q0);
        input  [3:0] d0;
        output q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
    

// add r1
        core_v core_vr1 ( d1, q1);
        input  d1;
        output q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
        end

//add r2
core_v core_vr2_i ( d2, q2);
        input  d2;
        output  q2;
       
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
      
        end

// add acc
core_v core_vacc( d, q);
        input  d;
        output q;
         reg [3:0] q;
        always @(posedge clk)
        begin
           if (ld==1) q <= d;
        end

//add temacc   
core_v core_tempacc(d3,q3 );
        input  d3;
        output q3;
        always @(posedge clk)
        begin
         if (ld==1) q <= d;
         end
     

// add accreg   
core_v core_tempreg(clk, ld, d4, q4);
        input  d4;
        output q4;
       
        always @(posedge clk)
        begin
           if (ld==1) q4 <= d4;
        end
    
//add alu  
core_v core_alu (z,a,b,sel);
input a, b;
input sel;
output z;

always@(sel,a,b)
begin
case(sel)
4'b0000: z=a+b;
4'b0001: z=a-b;
4'b0010: z=b-1;
4'b0011: z=a*b;
4'b0100: z=a&&b;
4'b0101: z=a||b;
4'b0110: z=!a;
4'b0111: z=~a;
4'b1000: z=a&b;
4'b1001: z=a|b;
4'b1010: z=a^b;
4'b1011: z=a<<1;
4'b1100: z=a>>1;
4'b1101: z=a+1;
4'b1110: z=a-1;
endcase
end
endmodule

kubeek · Sep 23, 2014

vead said:
line if (ld==1) q4 <= d4;
Error (10137): Verilog HDL Procedural Assignment error at core_v.v(70): object "q4" on left-hand side of assignment must have a variable data type

You cannot do assignement to something that is not a reg.

What exactly do you think this part does?

kubeek · Sep 23, 2014

vead said:
now I am getting only . 3 errors, 5 warnings

You already said that.

vead · Sep 24, 2014

ok I have rewrite code again
there are three registers that are connected with data bus
but I am getting error
Error: Node instance "comb_4" instantiates undefined entity "core_v0"
Error: Node instance "comb_19" instantiates undefined entity "core_v1"
Error: Node instance "comb_34" instantiates undefined entity "core_v2"

Code:

module core_v (clk, ld, d0,d1,d2,q0,q1,q2);
input clk ,ld;

// Input Port Declarations
input [3:0] d0 ;
input [3:0] d1 ;
input [3:0] d2 ;

// Output Port Declarations
output [3:0] q0;
output [3:0] q1;
output [3:0] q2;


// ports wire
wire [3:0] c0;
wire [3:0] c1;
wire [3:0] c2;

//add r0
core_v0 ( d0,q0,c0);
reg [3:0] q0;
always @(posedge clk)
begin
if (ld==1) q0 <= d0;
end

// add r1
core_v1 ( d1,q1,c1);
reg [3:0] q1;
always @(posedge clk)
begin
if (ld==1) q1 <= d1;
end
//add r3
core_v2 ( d2,q2,c2);
reg [3:0] q2;
always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
           end

endmodule

but I am getting error

Code:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Thu Sep 25 02:54:52 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off core_v -c core_v
Info: Found 1 design units, including 1 entities, in source file core_v.v
    Info: Found entity 1: core_v
Critical Warning (10846): Verilog HDL Instantiation warning at core_v.v(21): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at core_v.v(27): instance has no name
Critical Warning (10846): Verilog HDL Instantiation warning at core_v.v(33): instance has no name
Info: Elaborating entity "core_v" for the top level hierarchy
Error: Node instance "comb_4" instantiates undefined entity "core_v0"
Error: Node instance "comb_19" instantiates undefined entity "core_v1"
Error: Node instance "comb_34" instantiates undefined entity "core_v2"
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 3 warnings
    Error: Peak virtual memory: 231 megabytes
    Error: Processing ended: Thu Sep 25 02:54:57 2014
    Error: Elapsed time: 00:00:05
    Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 3 warnings

kubeek · Sep 24, 2014

I hate to repeat myself, but what exactly do you think this part of your code is doing?

Code:

core_v core_vr0 ( d0, q0);
        input  [3:0] d0;
        output q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end

vead · Sep 24, 2014

kubeek said:
I hate to repeat myself, but what exactly do you think this part of your code is doing?

Code:

core_v core_vr0 ( d0, q0); input [3:0] d0; output q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end

I think it should be

Code:

module core_v core_vr0 ( d0, q0);
        input  [3:0] d0;
        output q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
endmodule

kubeek · Sep 24, 2014

Almost. It should be:

Code:

module register(clk, ld, d0, q0);
        input  [3:0] d0;
        input clk;
        input ld;
        output [3:0] q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
endmodule

and it should be in its own file.
Then in the core_v module you make three instances of it, connected to the appropriate wires.

vead · Sep 24, 2014

kubeek said:
Almost. It should be:

Code:

module register(clk, ld, d0, q0); input [3:0] d0; input clk; input ld; output [3:0] q0; always @(posedge clk) begin if (ld==1) q0 <= d0; end endmodule

and it should be in its own file.
Then in the core_v module you make three instances of it, connected to the appropriate wires.

tell me what's wrong in this code it come with 5 error

Code:

module core_v (clk, ld, d0,d1,d2,q0,q1,q2);

input clk;
input ld;
// Input Port Declarations
input [3:0] d0 ;
input [3:0] d1 ;
input [3:0] d2 ;

// Output Port Declarations
output [3:0] q0;
output [3:0] q1;
output [3:0] q2;


// ports wire
wire [3:0] c0;
wire [3:0] c1;
wire [3:0] c2;

core_r0 (clk,ld,d0,q0,so);
endmodule 

  core_r1 ( clk,ld,d1, q1,s1);
endmodule
  core_r2 ( clk, ld,d2, q2,s2,);
endmodule
//add r0
module r0 (clk,ld, d0, q0);
        input  [3:0] d0;
        output q0,clk;
         reg [3:0] q0;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
    
endmodule

// add r1
        module  r1 (clk,ld, d1, q1);
        input  d1;
        output q1,clk;
         reg [3:0] q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
        end
        endmodule

//add r2
module r2 ( clk,ld,d2, q2);
        input  d2;
        output  q2;
        reg [3:0] q2;
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
      
        end

endmodule

endmodule

error

Code:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Thu Sep 25 06:07:44 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off core_v -c core_v
Error (10170): Verilog HDL syntax error at core_v.v(27) near text "(";  expecting ".", or an identifier, or "["
Error (10170): Verilog HDL syntax error at core_v.v(27) near text ")";  expecting ";", or ","
Error (10839): Verilog HDL error at core_v.v(27): declaring global objects is a SystemVerilog feature
Info: Found 0 design units, including 0 entities, in source file core_v.v
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
    Error: Peak virtual memory: 223 megabytes
    Error: Processing ended: Thu Sep 25 06:07:45 2014
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings

kubeek · Sep 24, 2014

You still dont get it, do you. Why do you make three different modules r1, r2 and r3 when they are the same? Make just one definition in another file and use it three times in core_v.
Also why do you have endmodule completely out of place near the line 27?
And, in case you cant see it, you have a comma in there that should not be there.

kubeek · Sep 24, 2014

look again at post #15 an do it just like it is in there. Fulladder would be your core_v adn halfadder would be the register. See how in fulladder I am using two instances of halfadder, called HA1 and HA2?

vead · Sep 24, 2014

kubeek said:
You still dont get it, do you. Why do you make three different modules r1, r2 and r3 when they are the same? Make just one definition in another file and use it three times in core_v.
Also why do you have endmodule completely out of place near the line 27?
And, in case you cant see it, you have a comma in there that should not be there.

sorry but still I don't understand why I am getting error
i have compiled your code but still getting error

Code:

module FullAdder(A,B,Cin,S,Cout);
  input A, B, Cin;
  output S, Cout;
  wire S1, C1, C2;

  HalfAdder HA1(A, B, S1, C1);
  HalfAdder HA2(S1, Cin, S, Cout);
  or Carry (Cout, C1, C2);
endmodule

error

Code:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Thu Sep 25 10:53:36 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FullAdder -c FullAdder
Info: Found 1 design units, including 1 entities, in source file FullAdder.v
    Info: Found entity 1: FullAdder
Info: Elaborating entity "FullAdder" for the top level hierarchy
Warning (10030): Net "C2" at FullAdder.v(4) has no driver or initial value, using a default initial value '0'
Error: Node instance "HA1" instantiates undefined entity "HalfAdder"
Error: Node instance "HA2" instantiates undefined entity "HalfAdder"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
    Error: Peak virtual memory: 231 megabytes
    Error: Processing ended: Thu Sep 25 10:53:40 2014
    Error: Elapsed time: 00:00:04
    Error: Total CPU time (on all processors): 00:00:03
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning

kubeek · Sep 24, 2014

Do you have both the parts loaded in quartus?

kubeek · Sep 24, 2014

Ok had a few bugs in there, here is the correct version.

Code:

module HalfAdder (A,B,S,C);
  input A,B;
  output S,C;

  xor sum (S,A,C);
  and Carry(C,A,B);
endmodule

Code:

module FullAdder(A,B,Cin,S,Cout);
  input A, B, Cin;
  output S, Cout;
  wire S1, C1, C2;

  HalfAdder HA1(A, B, S1, C1);
  HalfAdder HA2(S1, Cin, S, C2);
  or Carry (Cout, C1, C2);
endmodule

vead · Sep 24, 2014

kubeek said:
Do you have both the parts loaded in quartus?

w

kubeek said:
Do you have both the parts loaded in quartus?

when I paste both part there is no error
but when I compile following code i am getting error

Code:

module FullAdder(A,B,Cin,S,Cout);
  input A, B, Cin;
  output S, Cout;
  wire S1, C1, C2;

  HalfAdder HA1(A, B, S1, C1);
  HalfAdder HA2(S1, Cin, S, C2);
  or Carry (Cout, C1, C2);
endmodule

Code:

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition
    Info: Processing started: Thu Sep 25 11:49:30 2014
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FullAdder -c FullAdder
Info: Found 1 design units, including 1 entities, in source file FullAdder.v
    Info: Found entity 1: FullAdder
Info: Elaborating entity "FullAdder" for the top level hierarchy
Error: Node instance "HA1" instantiates undefined entity "HalfAdder"
Error: Node instance "HA2" instantiates undefined entity "HalfAdder"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings
    Error: Peak virtual memory: 231 megabytes
    Error: Processing ended: Thu Sep 25 11:49:31 2014
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 4 errors, 0 warnings

tshuck · Sep 24, 2014

when I paste both part there is no error
but when I compile following code i am getting error

........and how many files do you have?

Do you have both FullAdder.v and HalfAdder.v in your project?

vead · Sep 24, 2014

finally I made some code with no error

Code:

module core_v (clk, ld, d0,q0);
// Input Port Declarations
input clk;
input ld;
input [3:0] d0 ;
wire [3:0] c0;
// Output Port Declarations
output [3:0] q0;
reg [3:0]q0;
  always @(posedge clk)
   begin
     if (ld==1) q0 <= d0;
end
endmodule 
module registerr1(clk,ld,d1,q1);
input [3:0] d1 ,clk,ld;
output [3:0] q1;
wire [3:0] c1;
reg [3:0]q1;
        always @(posedge clk)
        begin
           if (ld==1) q1 <= d1;
           end
endmodule   
module register2 (clk,ld,d2,q2);
input [3:0] d2,clk,ld ;
output [3:0] q2;
wire [3:0] c2;
reg [3:0]q2;
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
           end     

core_v r0 (clk,ld,d0,q0,s0);
core_v r1 (clk,ld,d1q1,s1);
core_v r2 (clk,ld,d2,d2,s2);
 
endmodule

report

Code:

Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 7 warnings
    Info: Peak virtual memory: 260 megabytes
    Info: Processing ended: Thu Sep 25 12:58:17 2014
    Info: Elapsed time: 00:00:05
    Info: Total CPU time (on all processors): 00:00:04

kubeek · Sep 25, 2014

Over sixty posts, and you still have no clue. Please answer these questions:
Why is there definition of module "registerr1" when it is not used at all?
Why do you have three modules in one file? That is a bad practice and adds to your confusion. Keep it one module, one file.
Why do you have that allways block inside "register2"? What should it do?

vead · Sep 25, 2014

kubeek said:
Over sixty posts, and you still have no clue. Please answer these questions:
Why is there definition of module "registerr1" when it is not used at all?
Why do you have three modules in one file? That is a bad practice and adds to your confusion. Keep it one module, one file.
Why do you have that allways block inside "register2"? What should it do?

I think here is answer, this is new code without error

Code:

module core_v(clk, ld, d0, q0,d1,q1,d2,q2);
        input  [3:0] d0,d1,d2;
        input clk;
        input ld;
        output [3:0] q0,q1,q2;
        reg [3:0]q0,q1,q2;
        always @(posedge clk)
        begin
           if (ld==1) q0 <= d0;
           end
        always @(posedge clk) 
           begin
           if (ld==1) q1 <= d1;
           end
        always @(posedge clk)
        begin
           if (ld==1) q2 <= d2;
           end
endmodule

kubeek · Sep 25, 2014

See how the three allways blocks work exactly the same way? You are supposed to write them just once and call it a register, and then use it in three times in core_v.
If you dont understand what I meant then just ask.

vead · Sep 25, 2014

kubeek said:
See how the three allways blocks work exactly the same way? You are supposed to write them just once and call it a register, and then use it in three times in core_v.
If you dont understand what I meant then just ask.

you mean this type

Code:

always @(posedge  clk )
        begin
           if (ld==1) q0 <= d0;
           end
         
           begin
           if (ld==1) q1 <= d1;
           end
       
        begin
           if (ld==1) q2 <= d2;
           end

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input and output signal for microcontroller

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