Hi all,

In FPGA, how to use as a differential pair IO as a single ended IO. Especially, while drawing the hardware schematics, how to connect/use differential pair IO as a single ended IO for General purpose.

 

Hello there.
Differential logic families including
Low-Voltage Differential Signaling(LVDS), Low-Voltage
Positive Emitter-Coupled Logic, Bus LVDS, Gunning
Transceiver Logic, Gunning Transceiver logic plus, Centre
Tapped Terminated Logic, Pseudo Current Mode Logic, Point-
to-Point Differential signaling, Reduced Swing differential
signaling, Quad Rambus Signaling Levels, Transition-
minimized differential signaling, Differential Rambus
Signaling Level, I/O design parameters, GPIO, SPIO
Single-ended I/O standards (e.g., LVCMOS, LVTTL, HSTL, PCI, and SSTL)
• Differential I/O standards (e.g., LVDS, Mini_LVDS, RSDS, PPDS, BLVDS, and
differential HSTL and SSTL)
Below is a synopsis of the circuits involved.Use for reference only. please.

 

Hi all,

In FPGA, how to use as a differential pair IO as a single ended IO. Especially, while drawing the hardware schematics, how to connect/use differential pair IO as a single ended IO for General purpose.

Hi

First, I appreciate you might be being told to, but don't use schematics to design FPGAs ,

Most pins on most FPGAs are "programable", can be in our out , can be paired into a differential or used single ended, There are normally constraints on which pins can and can't be paired, as well as there are always some pins that can not be in or out, so you have to be aware of the chip your using,

The good thing, is the pins you want to use are defined in the tools by yourself as the configuration file and in your code
the tools will shout if you can not use the pins the way you intend ,
differential or a single ended primitive,

Personally , I don't use schematics, but HDL such as Verilog or VHDL, depending upon clients need.
but if you an give us some more information as to what tool chain your suing we might be able to help