Hi
I am designing a comparator at circuit level using CMOS 0.13um technology. The output of the comparator is shown in the attachment.
Here VP(V) is in the input voltage at the +ve terminal and VREF(V) is the reference voltage with which input is compared.
As we can the the ouput VQN(V) is oscillating. The principle of operation of the circuit is correct.
But whenever input is greater than reference, the output voltage keeps of swinging.
Can anyone please help me in this and tell me how to overcome this problem.
Input is 1V @ 5kHz and clock is 100kHz. VDD is 1V.
I have tried to implement other designs of the comparator too, but the output is identical to this one.
I am stuck on this problem from some time. it would be very kind of you if you could help me.
Thanks
I am designing a comparator at circuit level using CMOS 0.13um technology. The output of the comparator is shown in the attachment.
Here VP(V) is in the input voltage at the +ve terminal and VREF(V) is the reference voltage with which input is compared.
As we can the the ouput VQN(V) is oscillating. The principle of operation of the circuit is correct.
But whenever input is greater than reference, the output voltage keeps of swinging.
Can anyone please help me in this and tell me how to overcome this problem.
Input is 1V @ 5kHz and clock is 100kHz. VDD is 1V.
I have tried to implement other designs of the comparator too, but the output is identical to this one.
I am stuck on this problem from some time. it would be very kind of you if you could help me.
Thanks