How to remove Oscillations in CMOS based comparator ouput

Thread Starter

suhaibatt

Joined Apr 11, 2016
6
Hi

I am designing a comparator at circuit level using CMOS 0.13um technology. The output of the comparator is shown in the attachment.
Here VP(V) is in the input voltage at the +ve terminal and VREF(V) is the reference voltage with which input is compared.
As we can the the ouput VQN(V) is oscillating. The principle of operation of the circuit is correct.
But whenever input is greater than reference, the output voltage keeps of swinging.
Can anyone please help me in this and tell me how to overcome this problem.
Input is 1V @ 5kHz and clock is 100kHz. VDD is 1V.

I have tried to implement other designs of the comparator too, but the output is identical to this one.
I am stuck on this problem from some time. it would be very kind of you if you could help me.

Thankscomp3-2.jpg
 

SLK001

Joined Nov 29, 2011
1,543
Where is your schematic? You really expect us to look at your signals and be able to troubleshoot your issues?
 

Thread Starter

suhaibatt

Joined Apr 11, 2016
6
yes these are simulation results and regarding the rise time, I had used the same to test a sample CMOS inverter circuit and it worked properly.
 

Roderick Young

Joined Feb 22, 2015
408
1 nS rise time is more than reasonable for 130 nm technology. Is this a sense amp for a memory?

What is the purpose of the clock? Are you trying to save power or something? It seems that when the clock goes low, both Q and Q_not will be forced into an invalid state. If you need to latch the output, I'd say do your latching after the comparator. Or, be sure that you carefully sample the comparator results only with a fixed setup time after the rising edge of the clock. If you do not have a higher frequency clock on the die, you might be able to just use a few inverters as a delay. I wouldn't recommend that kind of thing for a board level design, but on a chip, every pS matters.
 

SLK001

Joined Nov 29, 2011
1,543
If the results are from a simulation, they you probably have two or more meta states. For instance, your MP5 and MP6 and MN15 and MN16 switch at the same time. One drain is going up while another is going down and both drains drive the output. You may be able to fix it with some delay circuit.
 

Thread Starter

suhaibatt

Joined Apr 11, 2016
6
Thanks for your insights Roderick and SLK001
Yes I am trying to latch the output and save as much power as I can in this whole process. I will try to add some delay in the circuit and see the results and let you know.....
 

Roderick Young

Joined Feb 22, 2015
408
Thanks for your insights Roderick and SLK001
Yes I am trying to latch the output and save as much power as I can in this whole process. I will try to add some delay in the circuit and see the results and let you know.....
What I suggest is that you run the output of your comparator into the D input of a static flip flop. The flip flop would then be clocked with a delayed version of your comparator clock, to allow enough time for the comparator to output a correct result.

If you're trying to save as much power as possible, what you really want is a narrow pulse going into the comparator - that is, only turn it on when it needs to be on. As shown, the comparator is on 50% of the time, when it likely only needs to be on for a few nanoseconds each time, just enough to take a measurement and latch the answer in the flip flop. The flip flop will not burn much power, of course, especially at 100 kHz.
 
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