How do I connect multiple 8255s to an 8085?

Thread Starter

keiichicom

Joined Apr 26, 2022
13
Hi,

I am ok on connecting one 8255 i/o chip to an 8085 mpu with an 74138 3 to 8 decoder chip but I am fuzzy on how to connect multiple 8255s? Can somebody please enlighten me, thanks?
 

Papabravo

Joined Feb 24, 2006
18,400
Hi,

I am ok on connecting one 8255 i/o chip to an 8085 mpu with an 74138 3 to 8 decoder chip but I am fuzzy on how to connect multiple 8255s? Can somebody please enlighten me, thanks?
You just have to look at more address bits to map them into distinct areas of memory. As long as no two devices occupy the same memory space you can add devices until the 64K of memory space is used up.
 

MrChips

Joined Oct 2, 2009
26,077
Circuit schematics is the language of electronics.

Try to match up the bus signals between the 8085 μP and the 8255 PPI peripheral while attempting to draw the schematics.
Every μP has three buses, address bus, data bus and control bus. Look to see what is common and what is unique.
Different peripheral devices must be assigned unique addresses. Hence the address bus must somehow select the different devices. This is the function of the 74138 decoder. Now look at the I/O operation and see what signals need to be activated in order to address a given peripheral.

This is a block diagram (not a circuit diagram) and is a good place to start.

8255 PPI - Parallel Peripheral Interface

1651891644195.png

If you need more help don't be afraid to ask.
 

Thread Starter

keiichicom

Joined Apr 26, 2022
13
Circuit schematics is the language of electronics.

Try to match up the bus signals between the 8085 μP and the 8255 PPI peripheral while attempting to draw the schematics.
Every μP has three buses, address bus, data bus and control bus. Look to see what is common and what is unique.
Different peripheral devices must be assigned unique addresses. Hence the address bus must somehow select the different devices. This is the function of the 74138 decoder. Now look at the I/O operation and see what signals need to be activated in order to address a given peripheral.

This is a block diagram (not a circuit diagram) and is a good place to start.

8255 PPI - Parallel Peripheral Interface

View attachment 266600

If you need more help don't be afraid to ask.
Thanks the explanation and diagram. It helps.
 

GetDeviceInfo

Joined Jun 7, 2009
2,095
although different devices, the IBM PC/XT technical reference manual is a classic document for anyone working with this family pf ICs.
IBM PC/XT

this machine had a coupe extra selects that were not implemented. I would stack a second 8255 onto the original, bending out the port pins for direct wire soldering, as well as the cs which took a spare decoder line. Otherwise it was soldered pin to pin.
 
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Thread Starter

keiichicom

Joined Apr 26, 2022
13
although different devices, the IBM PC/XT technical reference manual is a classic document for anyone working with this family pf ICs.
IBM PC/XT

this machine had a coupe extra selects that were not implemented. I would stack a second 8255 onto the original, bending out the port pins for direct wire soldering, as well as the cs which took a spare decoder line. Otherwise it was soldered pin to pin.
Thanks I will review it. I am using protoyping boards and soldering on male header pins, socketing all chips and discrete components, and using jumper wires for interconnections. Eventually I will design and order PCBs...
 

Papabravo

Joined Feb 24, 2006
18,400
The 8085 has a multiplexed Address/Data bus with A[7..0] multiplexed with D[7..0] so you must decode low order address bits from the address latch. In addition it has the control signal IO/M* which distinguishes memory accesses from I/O accesses. Some designers thought that memory mapped I/O was a good idea, but others were not so enamored of the concept. so it turns out you can accommodate 64K of memory AND 256 I/O addresses which are covered by the low order address bits which are available from the low order address latch. The schematic by Mr. Chips sows explicitly the IO/M* signal going to the decoder and the decoder output going to the 8259 and/or other peripheral chips.

For software I recommend you look up the BDS C-compiler by Leor Zolman. I believe he released into the public domain back in 2002. It is one helluva good piece of software.

https://en.wikipedia.org/wiki/BDS_C#:~:text=BDS C (or the BD Software C Compiler),old. "BDS" stands for "Brain Damage Software." ?msclkid=4de302a0cfc011ecb748aba19e0293f0
 
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