Homework on sequential circuits


Joined Feb 24, 2006
The definition of the D Flip-Flop is well known and understood. The behavior of the XOR gate and the inverter are also well known and understood. There may or may not be some ambiguity in the definition of the JK Flip-Flop behavior. It would help if you let us know how it is defined for your problem. If the JK Flip-Flop is designed as follows:

J=K=0 means HOLD present state
J=0,K=1 means CLEAR
J=1,K=0 means SET
J=K=1 means TOGGLE

Then the next state for A appears to be consistent with that definition.

Also, it would seem that the Flip-Flops change state on the rising edge of the clock. Is this correct?