Hey all, this is my first time posting here, and I was looking for some help from people better at electronics theory than I am to help me understand this Colpitts oscillator design, which was taken from this Wikipedia article: http://en.wikipedia.org/wiki/Colpitts_oscillator

Basically my group at school is working on their senior design project and I am largely responsible for a wireless power transfer system. I have a working oscillator simulation in LTSpice for my project which operates at about 151 KHz and is based on the model above with altered L and C values.

While that's great and all, I really don't understand some of how this circuit operates and am seeking help. My understanding is that R3 and R2 are set at 10k each in order to maintain a voltage of 3V at the base of the transistor for biasing. The feedback for the transistor is the voltage of C2, while the output for the circuit is the voltage across the series combination of C1 and C2.

So on to some questions:
1) The positioning of the inductor is not in a typical spot relative to the capacitors that I am used to seeing. It doesn't look like a parallel tank circuit. Are these somehow in parallel in a way that I am not seeing?

2) What is the role of C3 in this circuit?

3) What is the role of R1 in this circuit?

4) I took a plot of the Voltage across the Base-Emitter junction and it looks like the transistor spends the vast majority of its time in the cutoff region. Aren't you supposed to bias a circuit like this so it spends no time in the cutoff region?

Sorry if these questions are really basic. I'm not very experienced with transistor based circuits. I've taken mostly power and controls courses. Thank you for any answers. I am heading to work, so if any extra information is needed I will post again ASAP.

Also, the reason I have a pulse input for the voltage source is due to LTSpice and difficulties with starting oscillators.

This is the voltage across the Base-emitter junction.

 

You'll notice that C2 & C3 form a capacitive voltage divider typical of the Colpitts topology. C3 is grounded on the low side. Keep in mind that Vcc (DC supply +ve) is effectively at AC (RF) ground potential. Hence the supply side of L1 may be regarded as RF ground. So L1 may be thought of as being in parallel with the series combination of C2 & C3.
The common tap on the C2/C3 divider is the RF feedback signal point to the emitter terminal on the common base amplifier.
It possibly comes as a surprise that the oscillating amplifier operates with the base-emitter biased beyond cut-off. But this is not unusual. It is a consequence of the non-linear operating mode in closed loop feedback. The means by which this steady state condition arises probably has something to do with minimal energy state. Note that in this mode the collector current flows in pulses at the operating RF frequency.

 

You'll notice that C2 & C3 form a capacitive voltage divider typical of the Colpitts topology. C3 is grounded on the low side. Keep in mind that Vcc (DC supply +ve) is effectively at AC (RF) ground potential. Hence the supply side of L1 may be regarded as RF ground. So L1 may be thought of as being in parallel with the series combination of C2 & C3.
The common tap on the C2/C3 divider is the RF feedback signal point to the emitter terminal on the common base amplifier.
It possibly comes as a surprise that the oscillating amplifier operates with the base-emitter biased beyond cut-off. But this is not unusual. It is a consequence of the non-linear operating mode in closed loop feedback. The means by which this steady state condition arises probably has something to do with minimal energy state. Note that in this mode the collector current flows in pulses at the operating RF frequency.

This clarified what I was most concerned about. Thank you!