this is the schematic for the DTL NAND gate in my lesson.
from what i understood from the explanation when the 2 inputs are both 0/low the diodes are on, but the transistor is in cutoff because the input only provides 0V for the base of the transistor. When the 2 inputs are in 5V/high the 2 diodes are off, but the VCC provides the needed voltage for the base of the transistor to put it in saturation.
if the 2 inputs are 0/low and the diode is on why can't the Vcc provide the necessary voltage for the base like what it does when the 2 inputs are 5v/high?
from what i understood from the explanation when the 2 inputs are both 0/low the diodes are on, but the transistor is in cutoff because the input only provides 0V for the base of the transistor. When the 2 inputs are in 5V/high the 2 diodes are off, but the VCC provides the needed voltage for the base of the transistor to put it in saturation.
if the 2 inputs are 0/low and the diode is on why can't the Vcc provide the necessary voltage for the base like what it does when the 2 inputs are 5v/high?
