Dear Forum,

I am looking to understand what would a SoC digital latch implementation look like if SoC wanted to latch a 32.768 KHz TCXO input and synchronize it to an online 19.2MHz clock in frequency and time (i.e. apply the 19.2MHz learning to the 32.768KHz timestamp) so that the 32.768KHz can be corrected to within +/- 1ppm (Assuming that the TCXO frequency accuracy spec +/- 5ppm)

Appreciate your insights/thoughts.

Thanks
Chandra

 

It sounds like you need a phase lock loop. Divide the 19.2Mhz by 9375 to get 2048 hz. divide the 32.768 Khz by 16 to get 2048 hz. Feed these two 2048 hz signals into a phase comparator and use the output to adjuat the frequency of the TCXO.

Les.