I have a similar question to click here. However, in my case i am using ne 555 for logic gate inverter . I have generated the complementary PWM and it works totally fine. My question is how to add a dead time between the pulses.

From click here, people suggests to use an RC network, how do I implement it into this?
Below attached my LT spice for reference and try to simulate in LT Spice

 

Don't see how to do that with 555s.

Below is the simulation of a non-overlapping clock circuit using two CMOS gate packages:
The non-overlap time is determined by the one R1C2 time constant.

 

Below is the simulation of a non-overlapping clock circuit using CMOS gates:
The non-overlap time is determined by the R3C1 and R1C2 time constants.
You can drive that from one 555 astable.

View attachment 254335

Hi there, I cant access the link, can you take a screenshot and upload it?

 

View attachment 254316
I have a similar question to click here. However, in my case i am using ne 555 for logic gate inverter . I have generated the complementary PWM and it works totally fine. My question is how to add a dead time between the pulses. View attachment 254317

From click here, people suggests to use an RC network, how do I implement it into this?
Below attached my LT spice for reference and try to simulate in LT Spice

Something like this.
Then invert either A or B to get a complimentary output.

 

Hi there, I cant access the link, can you take a screenshot and upload it?

Reposted in post #2.

 

Don't see how to do that with 555s.

Below is the simulation of a non-overlapping clock circuit using two CMOS gate packages:
The non-overlap time is determined by the one R1C2 time constant.

View attachment 254351

Hi , can you attach the LT Spice file for this and all the library files for my reference because the LT Spice does not have built in files for these logic gates. Thank you . And, is the CD410106B and CD4001B be used in high-frequency oscillator circuit and does it oscilllate very high frequency (maybe 100kHz) without its square waveform being distorted?

With your design that has 6 logic gate, does that mean i have to use 6 seperate ic's ?

 

can you attach the LT Spice file for this and all the library files

Below are the files for the CD4000 logic gates.
The zip files go in the sym folder.

is the CD410106B and CD4001B be used in high-frequency oscillator circuit and does it oscilllate very high frequency (maybe 100kHz) without its square waveform being distorted?

The rise and fall times variy with the supply voltage.
Typical values are shown below:
Operation at 100kHz should still give a good waveform.

With your design that has 6 logic gate, does that mean i have to use 6 seperate ic's ?

Look in the data sheets.
You will see there are multiple logic gates in each package so you need just two packages.

Below is the same functional circuit but constructed with all Schmitt-trigger NAND gates (regular NAND gates can oscillate when seeing the slow rise-time from the RC delay).
It still requires two IC packages but they are now both the same type.

 

Below are the files for the CD4000 logic gates.
The zip files go in the sym folder.
The rise and fall times variy with the supply voltage.
Typical values are shown below:
Operation at 100kHz should still give a good waveform.
View attachment 254395
Look in the data sheets.
You will see there are multiple logic gates in each package so you need just two packages.

Below is the same functional circuit but constructed with all Schmitt-trigger NAND gates (regular NAND gates can oscillate when seeing the slow rise-time from the RC delay).
It still requires two IC packages but they are now both the same type.

View attachment 254396

Hi, Thank you, where does the 4V Vdd connected to? Is it to power all of the IC chip?

 

where does the 4V Vdd connected to? Is it to power all of the IC chip?

Yes.
As noted on my schematic the IC power connections are not shown.
Below is a representative package pin layout.
VDD is +power and VSS is ground.

 

Yes.
As noted on my schematic the IC power connections are not shown.
Below is a representative package pin layout.
VDD is +power and VSS is ground.

View attachment 254454

Hi, as note in your schematic,all unused pins are grounded. Is it just a good pratise? I mean unused pins can be grounded or just leave it unconnected because it is almost the same thing right?

 

hi Mrs,
When using CMOS devices, it is common practice to ground all non-used Inputs, [not outputs]

If left unconnected, a high impedance CMOS input can assume a Hi or Lo and can be susceptible to electrical noise.

E

 

T

hi Mrs,
When using CMOS devices, it is common practice to ground all non-used Inputs, [not outputs]

If left unconnected, a high impedance CMOS input can assume a Hi or Lo and can be susceptible to electrical noise.

E

Thanks E

 

as note in your schematic,all unused pins are grounded. Is it just a good pratise? I mean unused pins can be grounded or just leave it unconnected because it is almost the same thing right?

No, it's not just good practice.
I stated to ground all unused inputs, not all unused pins.
For CMOS circuits, leaving then unconnected is not "almost" the same as grounding them.
CMOS inputs are very high impedance (look like a small capacitor) and can float to a voltage that can cause high internal currents and zap the device.

 

Hi

What frequency do you intend to operate the PWM?
The dead-time generator frequency will have to be much faster.
(The CD40106B can be used instead of CD4049B, but use one or the other, not both)

 

Hi

What frequency do you intend to operate the PWM?
The dead-time generator frequency will have to be much faster.
(The CD40106B can be used instead of CD4049B, but use one or the other, not both)


View attachment 254574

View attachment 254575

Hi, thank you for answering .You said just use CD40106B for high frequency right? Why in your diagram there is a combination of logic gate. Can all the circuit contain only logic gate from CD40106B(which you said can handle extremely high frequency). Frequency i wish is 1MHz

 

Hi, thank you for answering .You said just use CD40106B for high frequency right?

No. I wouldn't recommend higher than 100khz

Why in your diagram there is a combination of logic gate. Can all the
circuit contain only logic gate from CD40106B(which you said can handle extremely high frequency).

No, I didn't say it could handle extremely high frequency. The circuit requires the logic gates I've shown. The dead time delays are obtained using the propagation delays of the inverters instead of RC components.

Frequency i wish is 1MHz

Then you should use a higher speed logic family like the 74HC/HCT devices.
However, they are limited to supply voltage of 5-6v

 

No. I wouldn't recommend higher than 100khz

No, I didn't say it could handle extremely high frequency. The circuit requires the logic gates I've shown. The dead time delays are obtained using the propagation delays of the inverters instead of RC components.


Then you should use a higher speed logic family like the 74HC/HCT devices.
However, they are limited to supply voltage of 5-6v

Hi, does the HC or HCT means high frequency?

 

hi Mrs,
Check this link and PDF.
E
https://electronicsclub.info/74series.htm

 

Hi, does the HC or HCT means high frequency?

HC = High speed CMOS
HCT = High Speed CMOS/TTL compatible.

I don't know your definition of "high frequency".
The max operating frequency varies, but generally, the HC/HCT max operating frequency is about 10-25Mhz Max.