Gate delays

Thread Starter

Fatima Rashd

Joined Dec 27, 2015
Assume that tpd is the average of tPHL and tPLH. Find the delay from each input to the output in the circuit shown below by

(a) Finding tPHL and tPLH for each path, assuming tPHL = 0.20 ns and tPLH = 0.36 ns for each gate. From these values, find tpd for each path.

(b) Using tpd = 0.28 ns for each gate.

(c) Compare your answers from parts (a) and (b) and discuss any differences.
The answer is given as:
tPHL-C,D to F = 2 tPLH + 2tPHL = 2(0.36) + 2(0.20) = 1.12 ns
tPLH-C,D to F = 2tPHL + 2tPLH = 2(0.20) + 2(0.36) = 1.12 ns.
Please anyone explain the answer.Thank You.


Joined Mar 31, 2012
So how about:

1) Showing the circuit that this problem is about (the crystal balls we all got for Christmas are still charging).
2) Showing YOUR best attempt at an answer for each part.


Joined Mar 31, 2012
Don't worry about trying to understand the answer.

Forget that you have access to the answer.

Take YOUR best shot at answering the question as best you can. Be sure to include your reasoning. That way we can see what you are thinking and where you might be going wrong.


Joined Mar 31, 2012
It might help if you first described what t_PHL and t_PLH are. In doing so you might get some insight as to what conditions have to apply in order for the propagation delay from the C or D input to the F output to even be meaningful.