How to implement variable delays in a gate signal

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ElishaS

Joined Apr 29, 2021
2
Finding tphl and tplh for each path assuming tphl = 0.30 ns and tplh = 0.50 ns, for each gate. From these values, find tpd for each path.
(b) Using tpd = 0.40 ns for each gate,
(c) Compare your answers in part (a) and (b) and discuss any difference.
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Papabravo

Joined Feb 24, 2006
18,422
How can variable gate delays be created in which the delays vary linearly over 1/4 of a period?
I don't know how variable delays can be used in practice, but once upon a time we had a number of fixed delays using a tapped delay line. There were at least two types, acoustic and magneto strictive. It's probably been 50 years since I've last seen one. We also used them for variable storage, kind of like a small single track disc drive.
 

AnalogKid

Joined Aug 1, 2013
10,055
R-C network, 1000 metres of coaxial cable, XOR gate, FPGA, digital signal processor, 555, etc.

Signal amplitude
Minimum frequency
Maximum frequency
Minimum pulse width or duty cycle
Maximum pulse width or duty cycle
Minimum delay time
Maximum delay time

<duh>

ak
 

Deleted member 115935

Joined Dec 31, 1969
0
How can variable gate delays be created in which the delays vary linearly over 1/4 of a period?
Well, thats a very open ended question, with lots of specifics needed.

it all depends what sort of delay length you need, what accuracy , what for.

Example, the delay for 1/4 of a period could be for 6 hours, ( as in a day period )
or it could be nano seconds or less


Sorry , a bunch more details as to the background of the question would be of use.
 
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