There are so many ways that this project can run off the rails, the list is so long.

1) No circuit diagram available.
2) Power supply voltage is inadequate.
3) Power supply current is inadequate.
4) Power supply is noisy.
5) Missing power supply decoupling capacitors.
6) Bad protoboard connections.
7) Incompatible logic families.
8) Driving LEDs without proper drivers.
9) Floating inputs.
10) Bad ICs.
11) Wrong connections.
12) Incorrect design.

 

the information PaulDF has provided us is vague

we donno his backgrounds perhaps he misiterprets things

The answers he gave do not have anything to do with the questions we have asked

i doubt he has a schematic anywhere else but in his mind -- i can appreciate the effort tiling the digital device up on pin-boards ← but the very fact is a major source of error . . . \( \qquad \qquad \) . . . there's pretty much nothing anyone can do about it

?? tough the problems with HC should start above 70kHz (if the supply is weak and wonders below nominal at output transitions) and with LS above 2 to 5 MHz

 

you need to set up a debugging strategy to "catch" the source of your error

one way is to log your signals to PC - but the multi channel loggers are g.d. slow + such involves a precision timing of the logged "events" = your debugger comes 2-levels of difficulty more complex design that the one you debug . . .

Option.2 : draw exact diagram of your circuit and reason out the "glitch"
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i don't see any specific states involved to cascading the counter in question . . . although the d/s states smth. "/!\ max. 500ns CLK transition /!\" https://www.onsemi.com/pub/Collateral/MC74HC390-D.PDF (pg. 3 table - TIMING REQUIREMENTS (Input tr = tf = 6 ns) Maximum Input Rise and Fall Times 4.5V 500ns )
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is also why i pointed out the link to input stage e.g. it's important that you drive your very 1-st stage (LSB) with a proper digital signal
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