MOD NOTE: Split from the following thread:
https://forum.allaboutcircuits.com/threads/input-circuit-for-a-0-to-30-mhz-frequency-counter.205374/

What kind of input circuit you need depends on what it is driving - the input of the CD4510 and 74HC7930 (switchable?)?

These might help:
To > 100 MHz:
View attachment 342377

To 30 MHz:
View attachment 342378

Dick,

Can you elaborate more on the logic of frequency counting? I normally work with 16MHz to 20MHz MCUs, and would like to be able to count frequencies much higher, but it's escaping me as to how to make a circuit do it, that I can then input into the MCU. If this should be in a new thread, I apologizes, please let me know.

 

I will study these schematics, thank you. But again, can you elaborate on the concept of what is being done? I mean I understanding taking a high clock rate and dividing it to get lower clock rates, but going the other way, how to I get higher clock-rates? Don't be afraid to talk to me like I'm a small child.

I mean, let's say I divide a 20MHz rate into 10MHz. How then do I output that 10MHz pulse, and turn it back into a 20MHz pulse, or faster? Perhaps my question is not related so much to frequency counting as it is to increasing it for some other useful purpose.

 

let's say I divide a 20MHz rate into 10MHz. How then do I output that 10MHz pulse, and turn it back into a 20MHz pulse, or faster?

Please explain why you want to increase the frequency of a signal.

A frequency doubler is often done with a XOR gate. The delay function is a Resistor Capacitor (RC).

Search for PLL Phase Lock Loop for information on how to make a frequency that is related to you reference but is not the same frequency.

 

This thread split off from its original thread is way off track.

The original poster wanted a signal conditioner that will accept any periodic signal, maybe 0 to 10 V amplitude and provide a 5 V signal suitable for input to CMOS gates feeding a homebrew frequency counter. In other words, it should amplify a low amplitude signal for suitable logic input and clamp high amplitude signals to prevent circuit damage. The frequency of the input signal can be anything from 0 Hz to 30 MHz.

No frequency conversion is required.

 

GOOD!!! Keep this on track!!For a wide spread of inputs there needs to be first a clamp with a bit of a filter to assure that only the intended frequency is counted. So the two diodes clamp will limit the input ti between zero and Vdd. Also that 0.01 mfd filter cap. Or maybe 0.001mfd, depending on the anticipated frequency. Then a CMOS buffer, possibly a 74HC14, with a very small, possibly adjustable, bis to allow triggering on very low voltage waveforms.

 

In addition, to avoid the frustration of not being able to read the frequency of a low level signal, there needs to be an adequate gain stage.When the signal is only 50 millivolts on top of two volts DC it makes counting a challenge and a frustration.

 

To multiply a frequency by an integer value you can use a phase locked loop. The PLL oscillator runs at the higher frequency, which gets divided by some integer value and is phase locked to that lower frequency. The dividing integer is the multiplication of the reference frequency.