There are too many things wrong with your circuit.

Did someone not tell you that you cannot mix 74LSxx with 74HCxx?

The HC374 is in the decade 1 and 2 section of the circuit.
This section of the circuit is working fine.
The LS374 is in the decade 3 and 4 of the circuit.
This section of the circuit is properly as well.
The trouble is the pulse glitch at the input of decade 5.

 

I did not know that about the HC devices.
Suggestion for pull up resistor?

1-10k.

 

1-10k.

Thanks.

 

Thanks.

Here's an application note describing CMOS interfacing considerations. It's from RCA (I found it on the internet), but not the 1977 COS/MOS Integrated Circuits databook were I first saw it.

 

Here's an application note describing CMOS interfacing considerations. It's from RCA (I found it on the internet), but not the 1977 COS/MOS Integrated Circuits databook were I first saw it.

Thanks for the link.
I have the 1977 COS/MOS i.c. book on my computer.
I found it while looking for clock chips.

 

Hi everyone.
Made the changes to my project as pointed out by all of you. Thanks.
This is the updated photo.
The LEDs are showing 1252 Hz. 1.252KHz.
I’ll work on the full schematic after dinner.

 

I have the 1977 COS/MOS i.c. book on my computer.

Do you still have the URL? I'd like a PDF of that version. My hardcopy has seen better days.

 

Do you still have the URL? I'd like a PDF of that version. My hardcopy has seen better days.

If I do, I’ll post it for you.

 

The breadboards

(multiple) is the reason why there is no quality ones today - you bought all the good ones ((shout up me - stupid cat))

for my cube are from the 70's and are good quality.

you cannot mix 74LSxx with 74HCxx

there is more than one way to successfully do so -- as long you don't direct couple them http://www.dieet.unipa.it/macaluso/tutorials/Comparison LS-TTL HCMOS.pdf https://www.onsemi.com/pub/Collateral/AN-368.pdf.pdf

 

Are you sure you know what you are doing? Your answers are very vague and indirect.
Let us get some specific answers to the questions we are asking. Then we have a better chance of being able to understand your problem.
I stated "I am assuming you are using the counter as a binary counter and not a BCD counter."
You answered "The counters are decade counters. "
I know they are decade counters. I will ask more directly: Are you using the counters as a binary counters or BCD counters?
Where did you get the circuit from? Did you design it?
Are you absolutely sure the first four decades are working correctly?
From your comments, I still don't know what you mean by :"After that the last stage output sends a pulse to the fifth once every four gate times."
Do you mean that the fourth counter outputs a negative pulse on QD, pin 5 ? What exactly are the "gate times" you are referring to?
Regards,
Keith

 

Are you sure you know what you are doing? Your answers are very vague and indirect.
Let us get some specific answers to the questions we are asking. Then we have a better chance of being able to understand your problem.
I stated "I am assuming you are using the counter as a binary counter and not a BCD counter."
You answered "The counters are decade counters. "
I know they are decade counters. I will ask more directly: Are you using the counters as a binary counters or BCD counters?
Where did you get the circuit from? Did you design it?
Are you absolutely sure the first four decades are working correctly?
From your comments, I still don't know what you mean by :"After that the last stage output sends a pulse to the fifth once every four gate times."
Do you mean that the fourth counter outputs a negative pulse on QD, pin 5 ? What exactly are the "gate times" you are referring to?
Regards,
Keith

In HZ mode: 1 Hz. In KHz mode: 1KHz.
These are divided down for decade reset and transfer.

 

As I mentioned before, if you are using the counters as binary counters, you will get a positive pulse on QD on every fourth and ninth count. Are these the "glitches" you are referring to?
To use the counters as divide by ten, you need to OR all four outputs to give a negative pulse out on count zero to trigger the next decade. The output on QD will trigger the next decade twice for each count of ten. That I why I showed you the truth table and asked where you got the circuit from. If it really is wired as shown in your diagram, only the most significant counter is giving the correct output.
Regards,
Keith

 

As I mentioned before, if you are using the counters as binary counters, you will get a negative pulse on QD on every fourth and ninth count. Are these the "glitches" you are referring to?
To use the counters as divide by ten, you need to OR all four outputs to give a negative pulse out on count zero to trigger the next decade. The output on QD will trigger the next decade twice for each count of ten. That I why I showed you the truth table and asked where you got the circuit from. If it really is wired as shown in your diagram, only the most significant counter is giving the correct output.
Regards,
Keith

No.
The counters are 74390.
Dual decade counter.
I use the LEDs to save board space.
The circuit is my design.
The counters are cascaded output Qd is connected to the input of the next stage.
Each of the counters gives a 4-bit output that is connected to the latches.
The glitch I’m constantly mentioning is at the input of decade 5.
This glitch only happens when the count reaches 5000 Hz and above.
There is no pulse glitch at any frequency below 5000 Hz.

 

Do you really not understand what I explained to you above?
If your project is wired as shown in your diagram with the QD output of each decade connected to the input of the next decade IT WILL NOT WORK!!!!!
I am sorry but I am not able to help you because you do not answer my questions and you ignore everything I try to explain to you.
Good luck.

 

IT WILL NOT WORK

?really http://tinyurl.com/vthrngv ((something patience)) ... there might still be that when all lower counters transit their outputs - the power would be insufficient = put the 0.1µF back + multiple wire all power rails + put 10 to 22 µF randomly over your supply rails ...

 

Can you elaborate on what you mean by a "glitch"?
You say that the circuit shows correct frequency with an input signal from 0Hz to 4999Hz.
What happens after 4999Hz?
Do the lower decades continue to work?

 

?really http://tinyurl.com/vthrngv ((something patience)) ... there might still be that when all lower counters transit their outputs - the power would be insufficient = put the 0.1µF back + multiple wire all power rails + put 10 to 22 µF randomly over your supply rails ...

In the schematic PaulDF provided, he is using the output on pin 5 to drive the next stage. That will NOT work correctly.

 

In the schematic PaulDF provided, he is using the output on pin 5 to drive the next stage. That will NOT work correctly.

Ignore the circuit schematic in post #10. The labels and pin numbers do not match 74LS390.

 

Ignore the circuit schematic in post #10. The labels and pin numbers do not match 74LS390.

Then, as I stated, the counter shown in the schematic will not work.
I was simply stating a fact. All the information PaulDF has provided us is vague and inaccurate. The answers he gave do not have anything to do with the questions we have asked. I can not help someone who will not communicate.

 

We’re moving away from the issue.
None of the above comments are relevant to the 5KHz pulse glitch.

And you insist in not showing a complete schematic.

Waste of time.