Hello Everyone,

I am fairly new to this so please bear with me.

I have been looking at reducing the static power consumption in an IC, and have been mainly focussed to reduce the parasitics in the wiring in the BEOL. However, I was wondering that whether in the FEOL, on an n-type transistor (thin film transistor) level - is there a figure of merit to explore? I have looked into ring oscillators and single inverters but not sure if a single transistor KPI could add value and provide a reasonable reference in this scenario.

Thanks,
AJ

 

I don't recognize the acronyms you are throwing around. Could you define BEOL, FEOL, and KPI?

Is this an IC you are using? Or an IC you are designing?

 

I don't recognize the acronyms you are throwing around. Could you define BEOL, FEOL, and KPI?

Is this an IC you are using? Or an IC you are designing?

Sorry, yes I am looking to design an IC and looking to pick transistors and match it to the load but wonder if there is a metric that I can use from the transistor behaviour that can help point me in the right direction.

FEOL - front end of line (device level)
BEOL - back end of line (interconnection)
KPI - key performance indicators (Vt, Ion, Isat, mobility etc.)