p.s. is it possible for you to send me the spice file - can you attach that here?
Would make life easier for me to get started with the program and I can amend it as required ......

Yes...but the smart switch is not a real smart switch model. I made it using a existing mosfet model just for this thread. Give me a few minutes..

 

Thank you for all your effort - amazing!
Shouldn't make any really difference on the switch - why I just showed as mosfet for simplicity

The armed source will also be powered on at the same time as the power circuit - it has the quirk that when it is first powered on, it always comes on in the not-armed state.
So when power first applied the Not-R input (armed is high) means /q will be low.
Then when Not-R goes low, the device flips;
when not-R goes high it remains in that state.

Edit - Sorry I think I misunderstood - you're calling Vin the gate voltage!
But still don't understand the Vq & V/q responses in the timing diagram

V q & V /q is not showing correctly in your model - surely when power first applied to the flip-flop then q will be high and /q will be low;
then when the armed input (Reset) goes low, bottom gate will make /q high and so also make top gate flip to low out on q;
Not sure why it's why showing what it does in your timing diagram? it should look like I show in my last timing diagram


I think problem is that Vq is starting out low
That was the idea for the timing capacitor on the input of the top gate (0.1 is probably not big enough) - that would ensure that input starts at a low while is not charged
So at power-on Vq would have to be a 1; then it would be unchanged as the capacitor charges and Vq would still be high;
only when not-armed goes low will it flip over and then remain so

 

Thank you for all your effort - amazing!
Shouldn't make any really difference on the switch - why I just showed as mosfet for simplicity

The armed source will also be powered on at the same time as the power circuit - it has the quirk that when it is first powered on, it always comes on in the not-armed state.
So when power first applied the Not-R input (armed is high) means /q will be low.
Then when Not-R goes low, the device flips;
when not-R goes high it remains in that state.

Edit - Sorry I think I misunderstood - you're calling Vin the gate voltage!
But still don't understand the Vq & V/q responses in the timing diagram

V q & V /q is not showing correctly in your model - surely when power first applied to the flip-flop then q will be high and /q will be low;
then when the armed input (Reset) goes low, bottom gate will make /q high and so also make top gate flip to low out on q;
Not sure why it's why showing what it does in your timing diagram? it should look like I show in my last timing diagram


I think problem is that Vq is starting out low
That was the idea for the timing capacitor on the input of the top gate (0.1 is probably not big enough) - that would ensure that input starts at a low while is not charged
So at power-on Vq would have to be a 1; then it would be unchanged as the capacitor charges and Vq would still be high;
only when not-armed goes low will it flip over and then remain so

The digital models are good.
I think the problem is the arm signal is feeding back thru R2. Try changing R2 to 1N4148 diode (anode connected to NAND output, cathode connected to gate)

 

... I think the problem is the arm signal is feeding back thru R2.

Ahh, that may be it - although V /q is staying high, which means it's actually Vdd through R1 (and R2) that would have to be doing that.

I am truly grateful for your help, especially creating the model - if I could impose just a little bit further:
I can't get the model to run - It errors with

Could not open Library file C:\users\user01\Documents\LTspiceXVII\lib\cmp\standard.mos

I put that file from your zip into the cmp library but it still comes up with that error ?
(of course User01 is my own User directory)

 

Ahh, that may be it - although V /q is staying high, which means it's actually Vdd through R1 (and R2) that would have to be doing that.

I tried this and it worked. R1 is OK. Just change R2 to a 1N4148 diode.

I am truly grateful for your help, especially creating the model - if I could impose just a little bit further:
I can't get the model to run - It errors with


I put that file from your zip into the cmp library but it still comes up with that error ?
(of course User01 is my own User directory)

Edit the file "smartsw_nmos.txt"

Look for the line containing:
.lib C:\Users\user01\Documents\LTspiceXVII\lib\cmp\standard.mos
Change this path to:
.lib standard.mos

Then in LTspice, goto "Simulate->Control Panel->Netlist Options".
Check the checkboxes "Default Devices[*]" and "Default Libraries[*]" if not already checked.
then click OK.

Should work after that.

eT

 

Been learning how to work my way around LTspice - but huge thanks to @eetech00 for getting me going with the starting circuit loaded.

First thing I had to do was reverse the Varm so that it starts high, then switches low - the arm device always comes on with a Not-Armed signal, which is the very issue I needed to overcome.

The diode doesn't work - it needs to biased other way around in order to sink the gate to ground through the Nand; but that still doesn't do it when trying to make the logic work along with the armed signal
Then that word 'logic' actually registered and I had a Eureka moment
And didn't even need any extra components with those gates already unused and available!

It's now doing exactly what I wanted - and the LTspice was invaluable in getting it figured out.

Here's the final result

 

Then that word 'logic' actually registered and I had a Eureka moment
And didn't even need any extra components with those gates already unused and available!

It's now doing exactly what I wanted - and the LTspice was invaluable

Good job!

That actually was going to be my next suggestion..

Glad it worked..

eT

 

It was staring me in the face - sometimes you can't see the woods for the trees!
Thanks again!