FlipFlop-Latch - power up condition

Thread Starter

DEcosse

Joined Jan 26, 2011
15
Preface: I am using an automotive alarm as a remote trigger to enable/disable another circuit
The 'armed' state is a low output; the 'disarmed' state is 'open' (high from a pull-up) - this gives me a basic enable/disable signal for my circuit.
My problem is that when it powers on, it always powers on in the disarmed state; therefor even when it has been 'armed', if the power is removed and restored, it will re-energize in the disarmed state. (I can't do anything about this, the module is what it is).
I need to be able to overcome this so that I always have a 'disable' condition at power-on.
After it has been set to armed after initial power-on, it will control normally between the two states - it is only the default power-on that is a problem.

My thought is using a simple flip-flop as a latch for the initial power-on condition:
the S would be tied to the power rail; R would have a pull-up to rail and also connected to the Alarm output; (So the R input would be 1 for Dis-Armed and 0 for Armed)
The logic works so that at initial condition with both S & R =1 it would have Q at 1;
System then Armed - Reset then goes low, Q goes to 0
System then Dis-Armed - Reset then goes high, Q remains at 0
And then continuing as only the R can change from 0 to 1 to 0 and the Q output remains latched at 0

Latch Truth Table Requirement
Power On - Q=1
Armed Q=0
Disarmed Q=0
Armed Q=0

(I can then combine this logic with the Armed/Dis-Armed signal to give me correct Enable logic)

My Overall Truth Table Requirement
Power-on - Dis-armed - Disabled
Armed - Disabled
Dis-Armed - Enabled
Armed - Disabled
etc
It will always follow this sequence.

Correct so far as in the latched state after the initial Reset going low?

The question is what happens at power on when effectively S&R = 1 - how can I ensure that Q is high?
Can I just use a capacitor on S input to have it be 0 when power is applied then becoming 1 (so it would be S=0, R=1, Q= 1 at initial power-on, then becoming S=R=1, whereby Q would remain 1?)
After the initial power connection, S would remain high unless power removed, so it's only what happens when it is initially powered that is of consequence

Am I on the right thought train or totally off? :D
What other considerations would I need?

Any alternative suggestions to satisfy my requirement?
My follow-on circuit in in SMD - don't have a lot of available real estate left so the fewer components the better!
 

danadak

Joined Mar 10, 2018
4,057
The principal way this is done is with a component that uses
a pullup on a HiZ pin, and the pin is guaranteed to be in the
HiZ state during chip power up. Note the supply for the pullup must
be valid for this to work. In other words you must be able to
have a known logic V available if something downstream is relying
on valid logic signals while this part of system is powering up.

A PSOC can handle this, as well as handle the state machine,
it has a state machine wizard in the tool, PSOC creator, for implementing
sequential behavior. First you create a symbol for the component, then
use state machine wizard to create logic behavior. All GUI tools.

In some designs this is simple enough where no code has to be written,
all done in PSOC HW.


http://www.cypress.com/training/psoc-video-tutorial-series-how-create-custom-components

This is all single chip. Even has a debounce component inside for
pins/mechanical switches. Component list attached, a component
is a resource inside of PSOC. See attached list.


Regards, Dana.
 

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Thread Starter

DEcosse

Joined Jan 26, 2011
15
Thank you Dana - that was very interesting
If it could be done on the PSoC4 in an SOIC8 package it would be compact enough if I can get my head around how to use the software!!
Seems quite a bit overkill though for my simple application with a fair bit of learning to get there
 

ebp

Joined Feb 8, 2018
2,332
If I follow, it looks like what is required is to differentiate the power supply to the logic to set the flip-flop and differentiate the trailing edge of dis-armed to clear it (or just use ARMED to clear). Apply gating as required.

With an RS flip flop made with cross-coupled gates, assertion of both inputs will result in assertion of both outputs. e.g. if the FF is made with NAND gates, R & S are active-low and the outputs are active high; if R & S are both low, both outputs will be high. If both inputs are asserted and then deasserted simultaneously, the result is unpredictable. A particular instance of the circuit will probably be consistent, but you shouldn't count on it.

Power-on circuits that employ capacitors are actually quite difficult to make work properly under all conditions. If power goes off and stays off for some time (tens of milliseconds typically sufficient, but it depends on the circuit) then goes on and stays on for some time, things usually behave nicely. If you get short blips of power loss, the circuit may not reliably generate a valid reset signal because a capacitor which was charged while power was on is not adequately discharged while the power is off. A diode across the timing resistor can be helpful in creating a fast discharge path (e.g. cap to supply, R to ground, junction to input of gate - diode across R speeds discharge of cap when supply voltage drops; protection diode internal to IC will be in parallel, but care is required to prevent excessive current through it). If the power does not rise sufficiently fast, the differentiator cap may not pull the input sufficiently high to assert the logic level. For "best" reset signal reliability, a POR IC is often the way to go, though they are ridiculously expensive.
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
Thank you also for those inputs ebp

If I follow, it looks like what is required is to differentiate the power supply to the logic to set the flip-flop and differentiate the trailing edge of dis-armed to clear it (or just use ARMED to clear). Apply gating as required.
Yes - would use the first 'armed' event to clear the initial power-on state;
subsequent disarm/re-arm actions would not change the output state as long as the Set input remains High (which it should unless physically disconnected)


... With an RS flip flop made with cross-coupled gates, assertion of both inputs will result in assertion of both outputs. e.g. if the FF is made with NAND gates, R & S are active-low and the outputs are active high; if R & S are both low, both outputs will be high. If both inputs are asserted and then deasserted simultaneously, the result is unpredictable. A particular instance of the circuit will probably be consistent, but you shouldn't count on it.
I don't believe there should be any occasion of both inputs zero - S is always going to remain High and at power-on, we know that the Reset input (the device output status) is always going to be high at turn-on; then subsequently S will always be high and R will toggle between low and hi dependent on the device's input stimulus.

... If power goes off and stays off for some time (tens of milliseconds typically sufficient, but it depends on the circuit) then goes on and stays on for some time, things usually behave nicely. If you get short blips of power loss, the circuit may not reliably generate a valid reset signal because a capacitor which was charged while power was on is not adequately discharged while the power is off.
This is an automotive application and once initially connected, it would normally remain connected to battery continuously. Momentary drop-outs are unlikely - it's either going to have the supply physically connected or disconnected.
For that end, currently it's easy enough to just 'set' the device manually after it is first powered on by simply arming after power is first applied and it then functions as I require; but what I am trying to prevent is a situation where the battery could be disconnected when it was in a secure (armed) state and re-applied causing it to just come back on in dis-armed state, over-riding any requirement for the input stimulus from the transmitter. It's OK if the User is the one doing the battery disconnection and re-connection (say for maintenance or similar) but need to protect against a possible malfeasance.
Anyhoo, I would say momentary disconnects are not going to happen or be a concern.
 

danadak

Joined Mar 10, 2018
4,057
Smallest package is 28 pin, Cypress has been asked many times to
do real small pinout packages, so far no luck.

Regards, Dana.
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
What do you think guys?

I'm using a dual-Nand as the active-low Flip-flop - nothing really conducive I could find directly in an SMD package

When gate input is low the power device is off.

Initially (at t0 - power on) /S will be Low so Q will be High;
then as C charges so /S becomes 1, but Q will remain High;
So /Q should be low, so gate sinks through R6 and device is OFF;
When then 'armed', /R goes Low so /Q goes High - however gate now sinks through R7 so device is still OFF;
When then 'disarmed', /R goes High, but /Q remains High - gate will be high, so device turns ON;
When 're-armed' /R goes Low, /Q still remains High - again gate sinks low through R7 so OFF
So after initial turn-on and first '/Reset', should cycle between armed & disarmed without changing the state of the Latch, with the Power device directly following the input signal

Suggestions on value for the cap?
Should not need much - might not even be necessary but should ensure that at power-on /S is low, ensuring Q is 1 before it then toggles when /R goes high

Thoughts/comments/issues?
I'll probably go ahead & throw a bread-board together and see what happens unless anyone sees any gotchas


Power-up_Latch.png
 

eetech00

Joined Jun 8, 2013
3,146
Hi

What is the purpose of Q1?
What controls the armed input? A contact? Might need debouncing.
Don’t need R3 and R4.
Add 0.1uf bypass cap from chip +suppy pin to ground.
CD4093B would be a better choice for Nand gate.

eT
 
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Thread Starter

DEcosse

Joined Jan 26, 2011
15
Q1 is power switch
Typo on the NAND chip - 40107 - that device needs pull-up on the outputs which is why R3 & R4 are there.
Of course on the cap across the supply terminals
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
Appreciate the inputs
Yes, would have liked 4093-type - that was only dual I could find (& 12V supply too ...) - don't have real-estate for 14 pin
The armed input comes from solid-state switch - should be OK I believe
I'll try a prototype with the 40107 and see how it works
 

eetech00

Joined Jun 8, 2013
3,146
Appreciate the inputs
Yes, would have liked 4093-type - that was only dual I could find (& 12V supply too ...) - don't have real-estate for 14 pin
The armed input comes from solid-state switch - should be OK I believe
I'll try a prototype with the 40107 and see how it works
Hmm...could have also used a CD4013B FF instead of a 40107 to drive the Mosfet.
The mosfet doesn't require much gate current.

Also, If R4 is pull-up then you don't need R6 and R7. Mosfet gate can connect to NAND pin 5.
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
^ Edit - thanks again for making me look again at the 4093 - I was able to shoe-horn it in there - wasn't too bad as interconnects actually became easier and was able to get rid of those pull-ups too.

If R4 is pull-up then you don't need R6 and R7. Mosfet gate can connect to NAND pin 5.
Note that you can NOT connect the gate directly to pin 5 (earlier schematic) - otherwise if /Q was high (enable state) then you would be shorting directly to the Armed 'Low' Input on that transition; so R6 is definitely required, yes?
However much simpler now with the 4093 and indeed can get rid of R3, R4, R5 & R7 (from earlier schematic)

This I believe should do it
The unused inputs are tied to opposite rails simply for ease of interconnect in the layout

Power-up_Latch_4093.png
 

eetech00

Joined Jun 8, 2013
3,146
Hi

I wasn't sure on the output state for armed/disarmed.
The output state is low when armed and high when disarmed.
But did you mean the output state to the gate of the smart switch? Or the output state to the load?

Something like this?

NANDFF.png
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
Thank you- (sincerely appreciate you putting that much effort into it!! - I really must download that and teach myself to use it!!)
your simulation is correct for what you have drawn, but that won't work for what I need - the output device needs to cycle on and off with each subsequent disarm and re-arm;
so yes, your timing diagram is correct for circuit you have drawn, but once on, (as shown) he power switch will only turn off with power off (which is not what is required);
also important to note the condition at t0 (3 secs as per your diagram) ALWAYS has 'armed' High when power first applied until it is asked to go Low - you don't have that state in the simulation; (that is the very condition I'm trying to overcome) - so at the time V1 is turned on, the Varm will be opposite to what your timing diagram shows and both /Q and Out will be Low until it changes state on first a low, then the next high on Varm.
Again, my requirement is that when power is first applied that the power device is OFF regardless of the Arm/Disarm
Then the 'Armed' source needs to go directly to the gate of the Power device, because correctly as per your simulation, the /Q output is going to be unaffected by subsequent arm and disarm events. . .

Sorry - I should have been more explicit on the power device - it's actually a high-side Smart Switch that is enabled on with a high input on the enable (shown as the gate) and disabled (Off) with - I just drew as FET for simplicity
Arm is an active low out of the device and 'open' when dis-armed, only pulled high by the pull-up - it will go for long periods in either the armed or dis-armed state.
I previously had the trigger source (your V2) going directly to the enable input, with just a pull-up - this worked well, with the only issue being the power-on state of the trigger source device always being 'dis-armed' - otherwise it controlled as desired after the initial disarm.
(I don't believe it should need R5 per your diagram either)
If you could run the Simulation again as I had drawn that would be much appreciated - again I should teach myself to use it myself!

This is what Needs to - and what I think should happen as per my previous diagram
(please excuse my drawing edits - not an actual simulation)

View attachment 151656
 

Thread Starter

DEcosse

Joined Jan 26, 2011
15
Note that the armed source output is connected directly to the gate in my diagram (you didn't include this in yours)

So the logic is - at power on, the smart switch is off, because it's held low by the /q output (even though the not-armed signal itself will be 'open' or high)
(the gate voltage in this case will be set by the voltage divider of R1/R6 so gate will be at 12*10/110 = 0.9V)
Then when the armed signal goes low, that itself will hold the gate low taking the gate to 0V;
at the same time /q will reset and go high, but on gate side of R6 it will be low; so power device is still off;
then when not-armed transitions high again, /q will still remain high, but now the gate will be high (both sides of R6 in this case) - so device will be on;
on next armed cycle, /q still remains high but armed is low again ...... and so on.
the only time /q will inhib the gate (by /q being low) is when first powered-on when not-armed signal is high - after first low armed input and then regardless of subsequent armed or disarmed response, /q will remain high so gate will solely be controlled by the armed signal

If you can just add that link wire from the Armed signal directly to the gate in your previous drawing that should do it and you can run the sim (after changing the armed to be inverted from what you show in the timing diagram)
 
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Thread Starter

DEcosse

Joined Jan 26, 2011
15
p.s. is it possible for you to send me the spice file - can you attach that here?
Would make life easier for me to get started with the program and I can amend it as required ...... :D
 

eetech00

Joined Jun 8, 2013
3,146
Note that the armed source output is connected directly to the gate in my diagram (you didn't include this in yours)

If you can just add that link wire from the Armed signal directly to the gate in your previous drawing that should do it and you can run the sim (after changing the armed to be inverted from what you show in the timing diagram)
Attached.
Just ignore the TP component. Its just there to separate net names.

NANDFF2.png
 
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