This is the truth table from our text book for the videos on this site.. correct me if I'm wrong but, i thought that when u SET a flip Flop Q would go high and NOT Q would go low

 

It does - on a 7474 the SET and RESET inputs are negative (as it says in the text)

 

SET and RESET on a 74xx74 D-type flip-flop are ACTIVE LOW.
We would put a bar over S and R in logic diagrams to indicate this property.

 

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This is the truth table from our text book for the videos on this site.. correct me if I'm wrong but, i thought that when u SET a flip Flop Q would go high and NOT Q would go low

The symbol might be drawn this way. The set input is sometimes called PREset and the reset input is sometime called CLeaR. The circles, often called "bubbles", indicate a signal that is ACTIVE LOW, that is True when it is at the lower voltage level.

This is NOT a standard approach across all logic families, and you should develop the habit of checking the datasheet very carefully as you have done. Props for that.

 

It should be noted that the otherwise functionally identical 4013 has true (i.e. not inverted) set and reset inputs.

 

The reason standard TTL flip-flops have inverted Set and Reset inputs is to minimize the power the flip-flop uses in normal operation where the two inputs are high most of the time.
A TTL input requires no current when high but you must sink current when low.

 

The reason standard TTL flip-flops have inverted Set and Reset inputs is to minimize the power the flip-flop uses in normal operation where the two inputs are high most of the time.
A TTL input requires no current when high but you must sink current when low.

. . . and a CMOS input takes no power in either state.
I'd be curious if anyone knows why the 4000 series needed to reinvent all the part numbering, functionality and pinouts, rather than adopting them from the 74 series (as in the 74C series that never really took off).

 

I'd be curious if anyone knows why the 4000 series needed to reinvent all the part numbering, functionality and pinouts, rather than adopting them from the 74 series (as in the 74C series that never really took off).

I believe it was because the two logic series were developed somewhat around the same time and RCA did not what to just copy the TTL devices.
Also, many CMOS devices do not have a 74 TTL series equivalent.

 

I believe it was because the two logic series were developed somewhat around the same time and RCA did not what to just copy the TTL devices.
Also, many CMOS devices do not have a 74 TTL series equivalent.

Thanks. If they were contemporary that makes sense. I was under the impression that the original 74 series predated the 4000 series.
It's interesting that some of the more useful 4000-only devices such as 4017 and 4046 have reappeared as 74HC4017 and 74HC4046.

 

TTL gates use negative logic because that provides greater noise immunity.

 

TTL gates use negative logic because that provides greater noise immunity.

What "negative logic" and how would that improve noise immunity?

 

Negative logic means ACTIVE LOW, i.e. the function is triggered on a low level.

Positive logic TTL input would trigger on a 2V noise pulse.
Negative logic TTL input would required 4V noise pulse to trigger, i.e. the pulse has to fall from 5V to below 0.7V to trigger /S or /R.

 

Thanks. If they were contemporary that makes sense. I was under the impression that the original 74 series predated the 4000 series.
It's interesting that some of the more useful 4000-only devices such as 4017 and 4046 have reappeared as 74HC4017 and 74HC4046.

In particular the transmission gate was unique to CMOS with no TTL equivalent.

The following was gleaned from the web:

The 4000 series was introduced as the CD4000 COS/MOS series in 1968 by RCA as a lower power and more versatile alternative to the 7400 series of transistor-transistor logic (TTL) chips. The logic functions were implemented with the newly introduced Complementary Metal–Oxide–Semiconductor (CMOS) technology.​

​

In 1964, Texas Instruments introduced the SN5400 series of logic chips, in a ceramic semiconductor package. A low-cost plastic package SN7400 series was introduced in 1966 which quickly gained over 50% of the logic chip market, and eventually becoming de facto standardized electronic components.[4][5] Over the decades, many generations of pin-compatible descendant families evolved to include support for low power CMOS technology, lower supply voltages, and surface mount packages. ​

​

They were roughly contemporary, but somewhat earlier than I thought.

 

So the 7400 series was born the same year that I was! That's why I don't remember its introduction. I still wonder why the 4000 wasn't a quad 2-input NAND gate, and the 4074 wasn't a D-type flip-flop with negative-going SET and RESET input, just to keep the numbering system consistent.
Wouldn't a transmission gate be rather tricky to implement in bipolar technology? Something similar to the four-diode circuit that is used to switch RF signals, perhaps - (there must be a name for it, but it eludes me at the moment).

 

Positive logic TTL input would trigger on a 2V noise pulse.
Negative logic TTL input would required 4V noise pulse to trigger, i.e. the pulse has to fall from 5V to below 0.7V to trigger /S or /R.

I understand that, but since, in a normal logic circuit, the signals will likely be equally at a high or low, I fail to see how whether it is considered positive logic or negative logic makes any significant difference in the noise tolerance.
You still have to keep the noise level below that which will give a false trigger to either a high or low logic level.

 

I still wonder why the 4000 wasn't a quad 2-input NAND gate, and the 4074 wasn't a D-type flip-flop with negative-going SET and RESET input, just to keep the numbering system consistent.

I think, at that time, RCA did not want to copy anything that Texas Instrument was doing.
It's the NIH syndrome.

 

I understand that, but since, in a normal logic circuit, the signals will likely be equally at a high or low, I fail to see how whether it is considered positive logic or negative logic makes any difference in the noise tolerance.

High or low levels are not equally likely.
If you design an S-R flip-flop in a circuit, SET and RESET triggers could very intermittent.
For example, the /RESET function on a microprocessor circuit occurs only once, i.e. only on power ON.

 

High or low levels are not equally likely.

You still have to keep the noise level below that which cause an error in either the high or low logic level.

 

The /RESET signal on a large complex system might be connected to many subsystems and modules along long traces or even backplanes. You want to make sure it is very immune to noise. You would not want a flight control system on an aircraft to be reset by some random noise spike.

7400 TTL negative logic provides a 4V noise threshold as compared to a 2V positive logic pulse.

With CMOS logic, since the threshold voltage is ½Vs, there is no noise immunity advantage to positive or negative logic.

 

Thank u very much