Hi every body,
i am an electronices engineer keen to learn more about modern electronices,can any one please, send me a tutorial concerning fbga technology and boundary scan technique to test it.
thanks in advance

 

Wikipedia is a good start for Ball Grid Arrays

As for boundary scan, are you familiar with a testing method called "Scan Design" or "Scan Path Testing"? Scan Design is a testing technique that inserts a series of scan-registers between the various logic-blocks of an IC; in the form:

Registers--LogicBlock--Registers--LogicBlock​

I.e. The registers provide the inputs to the subsequent logic block and receive the outputs from the previous logic-block.

The inputs to the scan-registers are controller by multiplexers. When the registers are configured to operate in Normal mode the registers merely pass the inputs to the lsubsequent ogic-blocks. When the registers are configured to operate in Scan mode, the output from one register is connected to the input of another to form a scan-chain. In scan mode the inputs to the registers are serially put into the scan chain so that the input to the logic blocks is predetermined. The idea behind this kind of testing is that you can specify the inputs to each logic-block on an IC - thus increasing the observability and controllability of the test-program.

Boundary testing is an extension of this idea where the testing is extended beyond the chip-level to the board-level; i.e. testing the inputs to each IC on a board.

I would recommend that you look at CMOS VLSI Design by Weste and Harris, chapter 9. You could also look at the supporting website at http://www.cmosvlsi.com/

Dave

 

In addition to the information that dave has provided, you may want to take a look at the information at the following website.

http://www.jtag.com/main.php

With the ever increasing emphasis on smaller IC packages together with greater pinout densities (i.e. ball grid arrays), the old bed-of-nails technique of testing boards is often no longer practical.

This has lead IC manufacturers to look at ways of designing IC's that have provisions for testing built into the device. JTAG IEEE-1149.1 is one of the solutions that has been introduced to deal with the testing challenges presented by these smaller and denser packages.

As an individual just now entering into the world of electronics, You are certainly justified in seeking to learn more about boundary scan techniques as you are very likely going to be required to factor this type of testing into any circuits you desigin in the coming years.

hgmjr

 

Well the original problem with built in test (BIT) methods was the fact that chip-area had to be sacrificed to test-components; particularly with the Scan-Design method. As IC components have decreased in size, there has been a two-fold benefit of this method:
1. The chip-area allocated to the test components has decreased, because the components that make up the registers and multiplexers have decreased in size.
2. The percentage of chip-area allocated to test components compared to total chip-area has decreased dramatically.

Therefore, BIT methods have become increasing popular in modern VLSI circuit deisgn. The other problem associated with the Scan-Design method is the minor delay penalties incurred through extra components in the scan path. Again as the components have decreased in size they have also become increasingly faster in operation.

These structured test methods are replacing the more traditional ad-hoc methods in VLSI circuit testing, and the next step after BIT methods is Built-In Self Test (BIST) methods which employs the use of test-generator and analyser circuitry, which can be analysed using advanced signature analysis techniques allowing for automation of large portions of the testing procedure.

Dave

 

Hello, the one thing I can mention about BGA and FBGA is they are virtually impossible to remove or install without special tools. I'm not a gread fan of them but they do address the reflow issues other package technologies have with many fine leads.