Hello, I have tried to analyse this circuit from an exam in electronics. I forgot to add in the drawing that the Vt = -0,4, so the MOSFET is a PMOS, I assume it's in saturation.

1) Calculate the operating point.
It means finding all the currents and nodes in the DC steady-state circuit. So the capacitor C=1nF is considered as an open circuit, the sinusoidal voltage generator Vin is shorted to ground, the zener diodes Dz1 and Dz2 are considered as DC voltage batteries (the value varies from -4.3V to 0.7V depending on the configuration).

I start from the branch with the zener diodes. Dz1 is in reverse, Dz2 is in direct, so applying the KVL to the entire branch I will have:

10v - i*1k -4,3v - 0,7v = -1v (I solve for the current i, having R1 = 1k ohm)
i*1k = 6
i = 6mA, it is the current that flows in the entire branch.

To find the voltage Vx at the point where the branch is connected to the gate of the MOSFET:

Vx = 10v -i*R1 = 10V - 6V = 4V

Vx coincides with Vg, the Gate voltage of the MOSFET.

Vg = 4V;
Being a PMOS, the current flows from the source to the drain; the source in this case is grounded, so Vs = 0;
Vd is the voltage of the negative input L- of the op amp, which is equal to the voltage of the positive input L+ due to the virtual short circuit principle, so Vd = L- = L+ = -1V

I can now find the current flowing in the MOSFET and going to the resistor R in the negative feedback of the op amp:
Id = k(Vs - Vg- |Vt|)^2 = 5ma/V^2*(-4,4V)^2 = 96,8mA

The voltage in the resistor R in the feedback will be:
Vr =Id*R = 96,8mA * 25k = 2,25k
(I am not very confident in my numbers here, this seems too high)

Finally, the gain is

gm = (2*Id)/Vov = (0,09*2)/4,4= 0,04A/V

2) Find the F(jw)=Vo(jw)/Vi(jw)

Since there is a mosfet in the circuit, I cannot use the normal configurations: inverting configuration or non-inverting configuration, I must use the appropriate KCL and KVL at the nodes concerning the PMOS. The PMOS in this case becomes a dependent generator, Vi is considered on, the zener diodes are considered as short circuits, and the capacitor is considered for its 1/sC impedance. The voltage of L+ is zero, being at ground in AC, same thing for the +10V.

First calculate the impedance in the negative feedback of the amplifier
R//(1/sC) = .. = R/(1+RsC)
I consider the PMOS in Common Source configuration:

Vo = gm*Vsg*[R/(1+RsC)], I expand the Vsg voltage: Vsg = Vin - 0

So:

Vo = gm*Vin*[R/(1+RsC)],

Vo/Vin = gm*[R/(1+RsC)]

is it correct?

3) Bode diagrams:
I don't know how to represent the diagrams here, I briefly describe what I did. Taking the frequency response H(s)=Vo(s)/Vin(s), I applied the limit that tends for s->0, the result came out 1000, from here:
20log(1000) = 20*3 = 60db.

The limit of H(s) that tends for s-> ∞ gives me 0, in short the trend of the signal from the circuit is a low pass.
I only saw one pole

wp= 1/C=1/10^(-9) = 10^9 rad/sec.

In the graph of the module I will start from 60db on the y-axis, until reaching the pole
in the x-axis of the rad/s. Arriving at the pole, the signal drops constantly by 20dca.

In the phase graph, same trend but it will start from 0 on the y-axis, a decade before the pole begins to go down; a decade after the pole will stop going down and continue straight to the phase of -180°.

is it correct?

4) Provide the instantaneous Vc and given Vin = -1V*sca(t), calculate the trend of the voltage and represent in the graph:

the value of the Laplace transform of the step function is sca(t) =1/s.

limit of the time tending to infinity is equal to the limit of s tending to 0 of s*H(s)*[1/s) = H(s) = gm*R

limit of the time tending to zero p equal to the limit of s tending to infinity s*H(s)*[1/s) = 0

In short in the graph in the y I have the voltage Vo, in the x I have the time t

there will be a constant line from the left towards the -1V up to the y-axis, after which it will slowly rise towards 0 infinitesimally.


I kindly ask you to correct me in my steps and possibly also in the values I found please? Thanks and talk to you soon

 

It looks to me like a switchable amplifier that has been drawn wrongly to me.
I would have expected the non-inverting input and the zeners to connect to 0V and the amplifier to be supplied by V+ and V-. Then it would almost work. I say "almost" because the gain is only limited by Rds(on) of the MOSFET and would go to a huge value when the MOSFET was fully enhanced.

 

It looks to me like a switchable amplifier that has been drawn wrongly to me.
I would have expected the non-inverting input and the zeners to connect to 0V and the amplifier to be supplied by V+ and V-. Then it would almost work. I say "almost" because the gain is only limited by Rds(on) of the MOSFET and would go to a huge value when the MOSFET was fully enhanced.

Understood, however this is exactly the circuit I've been given and I'm aware these are potentially just theoretical circuits. This is the capacity that my exam will reach in terms of configuration and difficulty.
Anyhows my question is: are my steps in the circuit analysis pertinent or correct? What do I correct?

 

I would start my analysis by assuming that the MOSFET is off, and work out the op-amp output voltage on that basis.
As the symbol for the MOSFET is incorrect, I would first check that the source is connected to the op-amp and the drain to the Voltage source.
Then I would look at the voltage between the gate and source of the MOSFET, and determine whether it is on or off.
The gate is at -1V+0.6V+Vzener, and the source will be at the same voltage as the op-amp output which you have previously determined.
That would suggest to me that the gate is at a higher voltage than the source in which case a p-channel device would be off.

 

I would start my analysis by assuming that the MOSFET is off, and work out the op-amp output voltage on that basis.
As the symbol for the MOSFET is incorrect, I would first check that the source is connected to the op-amp and the drain to the Voltage source.
Then I would look at the voltage between the gate and source of the MOSFET, and determine whether it is on or off.
The gate is at -1V+0.6V+Vzener, and the source will be at the same voltage as the op-amp output which you have previously determined.
That would suggest to me that the gate is at a higher voltage than the source in which case a p-channel device would be off.

Great idea, I did the exercise again, but with a different hypothesis: the MOSFET is correct, just in triode region, the numbers make sense but the formula to find the current is different, and the mosfet in the AC region becomes a resistance r = 1/[2k*(Vsg - Vt)]
I'll post my entire new calculation tomorrow. Thank you for your insight, I feel I'm beginning to get everything right

 

If that really is a p-channel enhancement-mode MOSFET, then the gate voltage is above the source voltage, so it will be firmly turned off. There might be current through its body diode which would upset your calculations.

 

View attachment 351897

Hello, I have tried to analyse this circuit from an exam in electronics. I forgot to add in the drawing that the Vt = -0,4, so the MOSFET is a PMOS, I assume it's in saturation.

1) Calculate the operating point.
It means finding all the currents and nodes in the DC steady-state circuit. So the capacitor C=1nF is considered as an open circuit, the sinusoidal voltage generator Vin is shorted to ground, the zener diodes Dz1 and Dz2 are considered as DC voltage batteries (the value varies from -4.3V to 0.7V depending on the configuration).

I start from the branch with the zener diodes. Dz1 is in reverse, Dz2 is in direct, so applying the KVL to the entire branch I will have:

10v - i*1k -4,3v - 0,7v = -1v (I solve for the current i, having R1 = 1k ohm)
i*1k = 6
i = 6mA, it is the current that flows in the entire branch.

To find the voltage Vx at the point where the branch is connected to the gate of the MOSFET:

Vx = 10v -i*R1 = 10V - 6V = 4V

Vx coincides with Vg, the Gate voltage of the MOSFET.

Vg = 4V;
Being a PMOS, the current flows from the source to the drain; the source in this case is grounded, so Vs = 0;
Vd is the voltage of the negative input L- of the op amp, which is equal to the voltage of the positive input L+ due to the virtual short circuit principle, so Vd = L- = L+ = -1V

I can now find the current flowing in the MOSFET and going to the resistor R in the negative feedback of the op amp:
Id = k(Vs - Vg- |Vt|)^2 = 5ma/V^2*(-4,4V)^2 = 96,8mA

The voltage in the resistor R in the feedback will be:
Vr =Id*R = 96,8mA * 25k = 2,25k
(I am not very confident in my numbers here, this seems too high)

Finally, the gain is

gm = (2*Id)/Vov = (0,09*2)/4,4= 0,04A/V

2) Find the F(jw)=Vo(jw)/Vi(jw)

Since there is a mosfet in the circuit, I cannot use the normal configurations: inverting configuration or non-inverting configuration, I must use the appropriate KCL and KVL at the nodes concerning the PMOS. The PMOS in this case becomes a dependent generator, Vi is considered on, the zener diodes are considered as short circuits, and the capacitor is considered for its 1/sC impedance. The voltage of L+ is zero, being at ground in AC, same thing for the +10V.

First calculate the impedance in the negative feedback of the amplifier
R//(1/sC) = .. = R/(1+RsC)
I consider the PMOS in Common Source configuration:

Vo = gm*Vsg*[R/(1+RsC)], I expand the Vsg voltage: Vsg = Vin - 0

So:

Vo = gm*Vin*[R/(1+RsC)],

Vo/Vin = gm*[R/(1+RsC)]

is it correct?

3) Bode diagrams:
I don't know how to represent the diagrams here, I briefly describe what I did. Taking the frequency response H(s)=Vo(s)/Vin(s), I applied the limit that tends for s->0, the result came out 1000, from here:
20log(1000) = 20*3 = 60db.

The limit of H(s) that tends for s-> ∞ gives me 0, in short the trend of the signal from the circuit is a low pass.
I only saw one pole

wp= 1/C=1/10^(-9) = 10^9 rad/sec.

In the graph of the module I will start from 60db on the y-axis, until reaching the pole
in the x-axis of the rad/s. Arriving at the pole, the signal drops constantly by 20dca.

In the phase graph, same trend but it will start from 0 on the y-axis, a decade before the pole begins to go down; a decade after the pole will stop going down and continue straight to the phase of -180°.

is it correct?

4) Provide the instantaneous Vc and given Vin = -1V*sca(t), calculate the trend of the voltage and represent in the graph:

the value of the Laplace transform of the step function is sca(t) =1/s.

limit of the time tending to infinity is equal to the limit of s tending to 0 of s*H(s)*[1/s) = H(s) = gm*R

limit of the time tending to zero p equal to the limit of s tending to infinity s*H(s)*[1/s) = 0

In short in the graph in the y I have the voltage Vo, in the x I have the time t

there will be a constant line from the left towards the -1V up to the y-axis, after which it will slowly rise towards 0 infinitesimally.


I kindly ask you to correct me in my steps and possibly also in the values I found please? Thanks and talk to you soon

The MOSFET is in saturation or not?
What do you consider as the behavior specs of the MOSFET when it is in saturation?

 

The MOSFET is in saturation or not?
What do you consider as the behavior specs of the MOSFET when it is in saturation?

That's part of the question, need to find if the mosfet is in saturation or not, had it been a current mirror or differential amplifier
then yes, in saturation of course, but here I have to figure it out as part of the exam question.
Condition for saturation ( for PMOS) is VDS ≤ VGS - VT and I'm verifying that

 

If that really is a p-channel enhancement-mode MOSFET, then the gate voltage is above the source voltage, so it will be firmly turned off. There might be current through its body diode which would upset your calculations.

I don't know why my teacher gave us such a tricky exercise.
So I spoke to my teacher and gave me the actual exam sheet with her numbers, you were right, it's a NMOS, silly me. Here are my calculations

the MOSFET is actually an NMOS with Vt=1V. Vd = 0V, Vs=-1V
Vg does not change, it is always Vg=4V, it is not in saturation but triode because the condition is valid
Vds<Vgs-Vt, is it correct?
Therefore the current in the mosfet will be found by:
Id = k[2*Vds (Vgs-Vt) -Vds^2] = 30*10^(-6)A, is it correct? This current is equivalent to that which passes through the resistance R, then calculating the voltage of R I will find Vo, being VR=Vo, correct?

For the frequency response Vo/Vi, given that the mosfet is in triode, can it be considered as a resistance r=1/[2k|Vgs - Vt|] ?
Always for the reason of the NMOS seen as resistance, can I use the inverting configuration to find the frequency response?
Vo/Vin = -[R//(1/sC)]/r , or
Vo/Vin =-(R/r)* [1/(1+RsC)].

To draw Bode diagrams, the limit for s tending to 0 of H(s) is 0db, the limit for s tending to infinity is minus infinity. I find a pole wp= 1/RC =4*10^4 rad/sec.
is a low pass; the module starts from 0db and drops meeting the pole wp. The phase starts from -180° and drops a decade before the pole and stops being affected by the pole a decade after the pole, dropping a total of -90°, arriving at-270°

Given vi(t) =-1v*sca(t), to find the analytical expression, I first find the Laplace of vi(t),
or Vin(s)=-1/s. With τ=R*C
I will do Vo(s)= H(s)*Vin(s)=(-1/(1+s τ))*(-1/s) = 1/s[1+s τ]

I find the inverse of 1/s[1+s τ] which would be:
Vo(t) =[1-e^(-t/ τ)]*sca(t).
with the limit of Vo(t) with t tending to 0 equal to 0
with the limit of Vo(t) with t tending to infinity equal to 1,
the graph (x=time; y= Vo(t)) will be an exponential that starts from the origin t=0s and will reach Vo(t)=1V as a maximum.
is this correct? Does my procedure make sense?

 

Did anyone every say what the zener voltage was?
Your teacher should study the correct symbols for MOSFETs.

 

Did anyone every say what the zener voltage was?
Your teacher should study the correct symbols for MOSFETs.

Reverse config. zener is -4,3V, while direct cofig zener is 0,7V (little drawing on the top right I drew of the test).
About the MOSFET symbol, yes I agree, but I guess she just took figuring out the mosfet as part of the challenge.

Anyhows, how was my approach this time?

 

Reverse config. zener is -4,3V, while direct cofig zener is 0,7V (little drawing on the top right I drew of the test).
About the MOSFET symbol, yes I agree, but I guess she just took figuring out the mosfet as part of the challenge.

Anyhows, how was my approach this time?

If the zener is 4.3V, then the two back-to-back zeners makes 5V.
So a MOSFET with the gate at 5V above the source is almost fully enhanced, and behave as a resistance equal to Rds(on).
So you've got an inverting amplifier with a gain of 25k/Rds(on) which is a huge amount that can't be determined accurately.

 

If the zener is 4.3V, then the two back-to-back zeners makes 5V.
So a MOSFET with the gate at 5V above the source is almost fully enhanced, and behave as a resistance equal to Rds(on).
So you've got an inverting amplifier with a gain of 25k/Rds(on) which is a huge amount that can't be determined accurately.

Yes, aside the zeners, shouldn't there be no gain in a MOSFET in a triode configuration and be treated as a resistor only? The test doesn't ask the gain's value either, only the Vo/Vin, hence would the employment of the inverter configuration (Vo/Vin = -Zf/Zin) for the Vo/Vin be enough? Everything is making more sense to me.
How about the Bode and the Analytical Expression?

 

I don't know why my teacher gave us such a tricky exercise.
So I spoke to my teacher and gave me the actual exam sheet with her numbers, you were right, it's a NMOS, silly me. Here are my calculations

the MOSFET is actually an NMOS with Vt=1V. Vd = 0V, Vs=-1V
Vg does not change, it is always Vg=4V, it is not in saturation but triode because the condition is valid
Vds<Vgs-Vt, is it correct?
Therefore the current in the mosfet will be found by:
Id = k[2*Vds (Vgs-Vt) -Vds^2] = 30*10^(-6)A, is it correct? This current is equivalent to that which passes through the resistance R, then calculating the voltage of R I will find Vo, being VR=Vo, correct?

For the frequency response Vo/Vi, given that the mosfet is in triode, can it be considered as a resistance r=1/[2k|Vgs - Vt|] ?
Always for the reason of the NMOS seen as resistance, can I use the inverting configuration to find the frequency response?
Vo/Vin = -[R//(1/sC)]/r , or
Vo/Vin =-(R/r)* [1/(1+RsC)].

To draw Bode diagrams, the limit for s tending to 0 of H(s) is 0db, the limit for s tending to infinity is minus infinity. I find a pole wp= 1/RC =4*10^4 rad/sec.
is a low pass; the module starts from 0db and drops meeting the pole wp. The phase starts from -180° and drops a decade before the pole and stops being affected by the pole a decade after the pole, dropping a total of -90°, arriving at-270°

Given vi(t) =-1v*sca(t), to find the analytical expression, I first find the Laplace of vi(t),
or Vin(s)=-1/s. With τ=R*C
I will do Vo(s)= H(s)*Vin(s)=(-1/(1+s τ))*(-1/s) = 1/s[1+s τ]

I find the inverse of 1/s[1+s τ] which would be:
Vo(t) =[1-e^(-t/ τ)]*sca(t).
with the limit of Vo(t) with t tending to 0 equal to 0
with the limit of Vo(t) with t tending to infinity equal to 1,
the graph (x=time; y= Vo(t)) will be an exponential that starts from the origin t=0s and will reach Vo(t)=1V as a maximum.
is this correct? Does my procedure make sense?

If you model the MOSFET as a current source, then it's a simple current. If you model the MOSFET as a constant resistance, then it's a resistor.
If the MOSFET is turned on very hard it is sometimes modeled as a pure resistance.

 

Yes, aside the zeners, shouldn't there be no gain in a MOSFET in a triode configuration and be treated as a resistor only? The test doesn't ask the gain's value either, only the Vo/Vin, hence would the employment of the inverter configuration (Vo/Vin = -Zf/Zin) for the Vo/Vin be enough? Everything is making more sense to me.
How about the Bode and the Analytical Expression?

Vo/Vin is the gain.
There will be a high-frequency roll-off at 1/2πRC at which point the phase will be 45°, just like any other inverting op-amp circuit.
As everything depends on Rds(on) which is an all-over-the-place value and highly temperature dependent, I wouldn't have thought any further anaylsis would be worth the bother.
The RC roll-off will dominate at high frequencies, so the effects of the MOSFET at high frequencies are inconsequential, but for a thorough analysis you would have to consider Rds(on) to be in parallel with its output capacitance, which would be dominated by Cgd.
At low frequencies there won't be much of interest.

 

If you model the MOSFET as a current source, then it's a simple current. If you model the MOSFET as a constant resistance, then it's a resistor.
If the MOSFET is turned on very hard it is sometimes modeled as a pure resistance.

Why did I read that with Yoda's voice haha. You are correct, though I think I have to consider the circuit ideally and not in a more practical view, for example the test specifically says so if we need to consider Early's voltage or not. In other practiced exams, another student considered also just putting a pure resistance if in triode or a dependant generator gm*Vgs if in saturation

Vo/Vin is the gain.
There will be a high-frequency roll-off at 1/2πRC at which point the phase will be 45°, just like any other inverting op-amp circuit.
As everything depends on Rds(on) which is an all-over-the-place value and highly temperature dependent, I wouldn't have thought any further anaylsis would be worth the bother.
The RC roll-off will dominate at high frequencies, so the effects of the MOSFET at high frequencies are inconsequential, but for a thorough analysis you would have to consider Rds(on) to be in parallel with its output capacitance, which would be dominated by Cgd.
At low frequencies there won't be much of interest.

Well I have to say that in our lessons Vo/Vin is taught as just the transfer function, while the gain of the circuit is found with the formula gm=(2*Id)/Voverdrive and that's found only in saturation zone. Does this make sense to you?

I get what you're saying but I should note that the test also says that it's a circuit meant to be studied in small signal equivalent AC (after finding the point of work in DC), so the temperature dependency you spoke about may not be considered here. The Bode graph describes the circuit as a low pass. The analytical expression describes an exponential function of Vo(t) that was flat until t=0seconds and reaches 1V with an exponential function.
The high-frequency you spoke about I think it's true but I don't think my teacher ever described anything like that during lessons for the course purposes.

Do I make sense? I'm sorry if there were any misunderstandings, I was going off by memory and didn't have the test sheet at hand till now and probably should've provided more details

 

You have the formula for the gain of the MOSFET. As the gate-source voltage remains constant throughout, the MOSFET is just a fixed resistor.

 

You have the formula for the gain of the MOSFET. As the gate-source voltage remains constant throughout, the MOSFET is just a fixed resistor.

Is that correct?
A model that uses 'gm' would consider the MOSFET to be a current source, and if the gate source voltage was constant then the MOSFET drain to source would be a constant current source not a resistance.

 

Why did I read that with Yoda's voice haha. You are correct, though I think I have to consider the circuit ideally and not in a more practical view, for example the test specifically says so if we need to consider Early's voltage or not. In other practiced exams, another student considered also just putting a pure resistance if in triode or a dependant generator gm*Vgs if in saturation

Oh that's funny, haven't watched that movie in years and years now.

Yeah since you seemed to be using the factor 'gm' I was thinking more in terms of a current generator than a constant resistance, but you have to decide that from the problem specifications. I'll read it over again later today.

 

Is that correct?
A model that uses 'gm' would consider the MOSFET to be a current source, and if the gate source voltage was constant then the MOSFET drain to source would be a constant current source not a resistance.

It doesn't actually matter, as Vgs is fixed, and above Vgs(th), and the input signal is on the drain terminal.