Calculate the time period of generated square wave for the given circuit. (Competitive Exam Question)

Thread Starter

vadakkodan

Joined Nov 6, 2019
16
Please find the attached , circuit screen shot.

The answer I assume is 12ns.
I'm trying to make a details study on this like these things,

1. I'm good at Tanner EDA software, I can do the schematics in the EDA tool and simulate it and can find the answer. But that is in my Windows machine and I don't want to open it any more. Which software you suggest as a best alternative for simulating some digital circuits? Which one you use for your kids?
2. Can you write a HDL code for this circuit? can we simulate this in Model/Questa Sim or Vivado or Quartus?


1574522165768.png
 

crutschow

Joined Mar 14, 2008
23,739
Which software you suggest as a best alternative for simulating some digital circuits? Which one you use for your kids?
My kids don't do circuit simulation :).
But several on these forums (including myself) use the free LTspice simulator from Analog Devices, which is one of the best free Spice simulators available..
You'd have to add a model for your gate, however.
 

SteveSh

Joined Nov 5, 2019
104
Please find the attached , circuit screen shot.

The answer I assume is 12ns.
I'm trying to make a details study on this like these things,

2. Can you write a HDL code for this circuit? can we simulate this in Model/Questa Sim or Vivado or Quartus?


View attachment 192267
You can write HDL code (Verilog, VHDL), but I'm not what you would get when you try to simulate it. Probably all XXX's (unknown), because the simulator does not know how to resolve the unknown initial condition.

When doing logic simulations (as opposed to timing), the simulator has no notion of time. It just evaluates logic functions according to boolean algebra.
 

Thread Starter

vadakkodan

Joined Nov 6, 2019
16
Why do you need a simulator or EDA tool? The answer can be determined with simple math.
I want to see it in detail, like how the signal glitches happening inside the chain system, I want to play with changing the time propagation delay timings etc., . I believe this kind of practice give little bit more power to my imagination on digital circuits.

May I know the answer for this question, if possible with a small explanation.
 

Thread Starter

vadakkodan

Joined Nov 6, 2019
16
My kids don't do circuit simulation :).
But several on these forums (including myself) use the free LTspice simulator from Analog Devices, which is one of the best free Spice simulators available..
You'd have to add a model for your gate, however.
I consider myself and the people who are all not living in Electronics main land are kids. So I asked like that Thanks for letting me know that you all guys use LTspice. Tried to simulate this, faced some issues, that's fine.
 

Thread Starter

vadakkodan

Joined Nov 6, 2019
16
You can write HDL code (Verilog, VHDL), but I'm not what you would get when you try to simulate it. Probably all XXX's (unknown), because the simulator does not know how to resolve the unknown initial condition.

When doing logic simulations (as opposed to timing), the simulator has no notion of time. It just evaluates logic functions according to boolean algebra.
I understand that simulators will not consider the time, but is there any way to do such time based analysis?
I want to see this written in HDL(Any) to form a schematic as exactly like the image drawn. I wrote simply like this but not correct.

module feedback(
input a,
output out);

wire a1,a2,a3,a4;

assign a1 = ~a;
assign a2 = ~a1;
assign a3 = ~a2;
assign a4 = ~a3;
assign a = a3;
assign out = a4;

endmodule
1574579214723.png
 

SteveSh

Joined Nov 5, 2019
104
I understand that simulators will not consider the time, but is there any way to do such time based analysis?
I want to see this written in HDL(Any) to form a schematic as exactly like the image drawn. I wrote simply like this but not correct.

module feedback(
input a,
output out);

wire a1,a2,a3,a4;

assign a1 = ~a;
assign a2 = ~a1;
assign a3 = ~a2;
assign a4 = ~a3;
assign a = a3;
assign out = a4;

endmodule
So, in order to do a timing simulation, you have to synthesize your HDL and target it (or instantiate it) to a specific device, like a Xilinx FPGA. Then you have to do a place-and-route, which is where the logic, flip flops, and interconnects are all put together to implement your design in the target device. It's at this point that the simulator and timing analysis tool can put together the vendors timing information for the part you are targeting and figure out what the actual delays through the circuit will be.

But even then I don't think you will see a square wave come out of your design because, like I said earlier, the simulator has no way to resolve the unknown states of the 3 inverters at the start of the simulation.

I also don't know if the simulator would even try to simulate your circuit, as these are digital simulators, not analog, and they may not be able to handle the feedback path in your circuit.

If you break the feedback path, then the timing simulator could properly evaluate the delay through the 3 inverters and their interconnects. But this delay would be highly variable, depending on voltages, temperatures, and normal part-to-part (process) variation.
 

crutschow

Joined Mar 14, 2008
23,739
Below is the LTspice simulation of three 74HC04 inverters for which I had a model:
I did have to use the .iC command to set one of the nodes initially to 0V to get a proper simulation.

1574613933113.png
 

SteveSh

Joined Nov 5, 2019
104
That looks reasonable. That's because LTSpice is at its heart an analog simulator, so it knows how to handle combinatorial feedback paths.
 
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