Hello,

I'm newbie in electronic and with LTspice usage.

I try to use XOR gate with dflop component.

My circuit is in attached file of this topic.

When i replace my XOR gate by AND gate or OR gate, it's work.

But when i use XOR gate, i have this error :

Analysis: Time step too small; time = 0.001, timestep = 1.25e-018:
trouble with dflop-instance a1

I don't understand why i have this error with XOR gate and not with AND gate.

Thank you for your help,

 

What exactly are you trying to do with the XOR gate?
I think the problem is that there's a conflict between the XOR output and what the FF is trying to do.
If you put a small RC delay between the XOR and the D input, it will simulate without error.

 

Hello,

I'm newbie in electronic and with LTspice usage.

I try to use XOR gate with dflop component.

My circuit is in attached file of this topic.

When i replace my XOR gate by AND gate or OR gate, it's work.

But when i use XOR gate, i have this error :

Analysis: Time step too small; time = 0.001, timestep = 1.25e-018:
trouble with dflop-instance a1

I don't understand why i have this error with XOR gate and not with AND gate.

Thank you for your help,

Add some prop delay to each device... about 2n using TD=2n parameter

 

To add the delay, right-click the component symbol and enter 'td=2n' in its Value field.

 

Thank you for your answers.

To add the delay, right-click the component symbol and enter 'td=2n' in its Value field.

I make a delay on XOR gate and it's work.

What exactly are you trying to do with the XOR gate?
I think the problem is that there's a conflict between the XOR output and what the FF is trying to do.
If you put a small RC delay between the XOR and the D input, it will simulate without error.

I try to make a 8 bits register and increment it for each clock cycle.

Why i must make a delay on XOR gate and not for AND gate ?

 

Why i must make a delay on XOR gate and not for AND gate ?

Look at the logic.
I believe you have a race condition.

Why do you think you need an XOR gate?
They are not usually used for that purpose.

 

Why i must make a delay on XOR gate and not for AND gate ?

Either could be delayed. The important thing is that both circuits shouldn't change state at exactly the same time, or Spice will get its knickers in a twist.

 

Look at the logic.
I believe you have a race condition.

Why do you think you need an XOR gate?
They are not usually used for that purpose.

Because XOR is used for make addition.

What do you preconise ?

I thought to do like this schema for increment a 2 bit register.

But i have always 0 in Q out of A3 and A2.