@eetech00, I appreciate the sim output!

As I haven't made the time to learn how to properly simulate my experiments yet, this will give me something to compare to and test against when I breadboard this later. Seriously, thanks!

Also, be aware there is a state where both Q and Qbar are high at the same time.

With at least one of the asynchronous inputs pulled low and unused, wouldn't that be effectively impossible?

 

@eetech00, I appreciate the sim output!

As I haven't made the time to learn how to properly simulate my experiments yet, this will give me something to compare to and test against when I breadboard this later. Seriously, thanks!


With at least one of the asynchronous inputs pulled low and unused, wouldn't that be effectively impossible?

It shouldn't happen with the way the CD4013B is circuited, but its good to be aware of the all the possible states the FF can have.
Some designers are surprised by that entry in the truth table.

 

CD4013s, and many other components, are made by many different companies and are quite different internally. For some, if both S and R are pulled high, both Q and Q(not) go high for the duration of the event. From other suppliers that does not happen.

 

CD4013s, and many other components, are made by many different companies and are quite different internally. For some, if both S and R are pulled high, both Q and Q(not) go high for the duration of the event. From other suppliers that does not happen.

A D-FF identified as part number "CD4013B" conforms to its datasheet truth table.
A D-FF that functions slightly differently will have a different part number regardless of the manufacturer.

 

A D-FF identified as part number "CD4013B" conforms to its datasheet truth table.
A D-FF that functions slightly differently will have a different part number regardless of the manufacturer.

Given that the operation with both S and R high is not a specified performance, that statement does not apply.
It is a great theory, but not always found in reality. THAT has been my experience. For some products we sold, not only the IC model, but also the manufacturer were always specified. Understand that only what is shown in the data sheet is claimed to be true. "Wishes" are seldom granted in the component real world. THAT was several times a conflict with one sales person at one company. Wanting something to be true does not make it true. (The unhappy truth there is that every wire has some resistance between it's ends.)

 

Given that the operation with both S and R high is not a specified performance

If it's in the spec sheet truth table for the device, how is that not "specified performance"?

Below from the TI data sheet:

 

Given that the operation with both S and R high is not a specified performance, that statement does not apply.
It is a great theory, but not always found in reality. THAT has been my experience.

I agree there may be performance differences, but I referred to a D-FF and its truth tables, not its performance characteristics or other devices. Give an example of a D-FF where what I've stated does not apply...

 

I agree there may be performance differences, but I referred to a D-FF and its truth tables, not its performance characteristics or other devices. Give an example of a D-FF where what I've stated does not apply...

Different manufacturers provide different data sheets. AND the different brands of CMOS one-shots certainly trigger differently. The reality is that the internal circuits are not the same, between different brands.

 

Different manufacturers provide different data sheets. AND the different brands of CMOS one-shots certainly trigger differently. The reality is that the internal circuits are not the same, between different brands.

No one is debating that.

 

@sghioto, a question about your RC differentiator values before the gate of the BS170 (47nF, 1M).

The spec in the datasheet for the TQ2-L2-9V says:

Operate (Set) time Max. 3 ms at rated coil voltage (at 20°C, without bounce)

[Max. 3 ms (at 20°C, without bounce)]

Release (Reset) time Max. 3 ms at rated coil voltage (at 20°C, without bounce, without diode)

The application notes say:

As a guide, make the minimum pulse width in order to set or reset a latching relay at least 5 times the set time or reset time of each product and apply a rectangular-wave rated voltage.

So, the minimum pulse width, according to the docs, would be 15ms.

Your 47nF/1M combo gives us a time constant of 47ms.

Did you choose 47nF/1M because it's two relays in parallel? So, it's roughly double the minimum but, perhaps, simply rounded up due to 47nF being a fairly common capacitor value?

 

So, the minimum pulse width, according to the docs, would be 15ms.

Your 47nF/1M combo gives us a time constant of 47ms.

Did you choose 47nF/1M because it's two relays in parallel? So, it's roughly double the minimum

You want a value higher than the minimum to insure the circuit will work with the worst-case tolerances of the resistors and capacitors.
A value higher than minimum is not a problem.

 

You want a value higher than the minimum to insure the circuit will work with the worst-case tolerances of the resistors and capacitors.
A value higher than minimum is not a problem.

Is there a rule-of-thumb involved here? Like, if the component tolerances are 5%, do you factor in an additional 10%?

I'm just trying to understand the reasoning behind certain value selections. As a noob, it seems that sometimes these sorts of decisions have more in common with alchemy than with science.

 

This is what I read:

 

Is there a rule-of-thumb involved here? Like, if the component tolerances are 5%, do you factor in an additional 10%?

I'm just trying to understand the reasoning behind certain value selections. As a noob, it seems that sometimes these sorts of decisions have more in common with alchemy than with science.

The RC delay is simply calculated as an "unloaded" delay. The actual time delay would depend on the load current pulled from the RC junction (which affects how fast the cap discharges). But since the load current is that pulled from the mosfet gate, it is insignificantly tiny, so really has no significant effect on delay. For all intent and purposes, it is 47ns.

 

I'm just trying to understand the reasoning behind certain value selections.

When a value is not critical or only has to be above or below a certain value, then typically you don't calculate tolerances involved, but just use a larger or smaller value that's well beyond the maximum or minimum required.
I often use 100% or more to make sure all part tolerances are sure to be included.