Driving a GPIO port and understand the current calculations to do so

Thread Starter

dmacauley

Joined Jan 6, 2021
7
Would someone please go through the calculation refresher for understanding if one digital 3.3V level port on device can drive a GPIO port on another device? I understand the voltage levels for Voh, Vol, Vih, Vil, etc but want to see how to calculate and understand if the driving port can drive the receiving port.
Please explain this such that I can use these calculations for other digital devices on 3.3V levels to know the drive capabilities are fine.
If you can provide the calculations and what I can use moving forward for other pins between devices, that would be most appreciated.

The port that is driving the signal is shown below. It sends out a positive pulse every second, so need to know it can drive both high and low.
1610026567492.png

The port receiving the signal is on the TI AM3358 processor GPIO port pin.

1610027117635.png
 

jpanhalt

Joined Jan 18, 2008
10,917

Thread Starter

dmacauley

Joined Jan 6, 2021
7
So, perhaps you can elaborate based on just looking at the two datasheets and their specs to tell me specifically how I know this can drive it or not? I'm looking for a more pinpointed answer of knowing how to calculate or know it will drive it or not.
 

jpanhalt

Joined Jan 18, 2008
10,917
Your driving chip is spec'd at 4 mA output:
1610032168574.png

We cannot tell from the snippet you post whether that is maximum or just the test condition for typical operation.

There are various configurations of the receiver chip, e.g., whether pullup or pulldown is enabled. Worst case for any of them does not exceed ±243 uA. Thus, your driver should be adequate. There may be come capacitance on the input (e.g., a mosfet gate). That may slow down the transition but not prevent it. Now, if you are trying to drive more than one (i.e., fanout >1), then you might need to consider that limit.
 

dl324

Joined Mar 30, 2015
12,212
Would someone please go through the calculation refresher for understanding if one digital 3.3V level port on device can drive a GPIO port on another device?
What is the total load on the driving port?

CMOS devices are generally designed to drive at least 10 standard loads. The limiter is how much capacitance can be driven. Edge transition times will be specified for a maximum capacitive load.
 

Thread Starter

dmacauley

Joined Jan 6, 2021
7
It is a single point to point connection on one GPIO on the receive side. The driver is for the PPS signal on the GPS chip. It is 3.3V level.

Receiver is on page 91.
https://www.ti.com/lit/ds/symlink/a...l=https%3A%2F%2Fwww.ti.com%2Fproduct%2FAM3358

Driving chip is on page 17
https://www.u-blox.com/sites/default/files/SAM-M8Q_DataSheet_(UBX-16012619).pdf

However, please elaborate about what doesn't exceed +/-243 uA.
If you don't mind breaking it down for me please.
What is the total load on the driving port?

CMOS devices are generally designed to drive at least 10 standard loads. The limiter is how much capacitance can be driven. Edge transition times will be specified for a maximum capacitive load.
 

Thread Starter

dmacauley

Joined Jan 6, 2021
7
I'm not sure we are actually connecting here. Can you break it down to simple terms of what you are saying? I understand and appreciate you are saying that this pin can drive the other device, but when it comes to a simple explanation of how you determined this, that is what I'm looking for.
 

Thread Starter

dmacauley

Joined Jan 6, 2021
7
What is the total load on the driving port?

CMOS devices are generally designed to drive at least 10 standard loads. The limiter is how much capacitance can be driven. Edge transition times will be specified for a maximum capacitive load.
Dennis, would you like to share any details?
 
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