I'm doing an alarm clock for my mid-term assignment. But I got a problem in the ripple counter. Somehow, the counter reset after the 39 and became 0 instead continue. This is my circuit.

 

hi 123,
Welcome to AAC.
Have you created a truth table for the counting and reset sequence that you could post.?
E

 

Your R inputs have no valid logic state.
Do not assume that an input pin with no connection is at logic LOW.

 

Your R inputs have no valid logic state.
Do not assume that an input pin with no connection is at logic LOW.

I know that. I want to reset after reach the 60 sec but it got reset at 40 sec without need R input.

 

hi 123,
Welcome to AAC.
Have you created a truth table for the counting and reset sequence that you could post.?
E

My idea is use 2 ripple counter with 4 bits. When it reach 1010 binary (10 as decimal). It will send a signal to reset the first counter and continue a second counter. Everything works fine until it reaches 40 sec. It got reset to 0 instead continue the counter.

 

hi 123,
What type are the JK flip/flop IC's?
TTL or CMOS
E

 

I'm doing an alarm clock for my mid-term assignment. But I got a problem in the ripple counter. Somehow, the counter reset after the 39 and became 0 instead continue. This is my circuit.
View attachment 295739

What is driving the reset on the lower group of flip flops? You are showing them floating, which is going to make them very twitchy.

The problem you are having is that you are designing an ad hoc asynchronous logic circuit without taking responsibility for properly vetting the design.

You are also trying to assert the J and K inputs with the same signal that you are trying to use for the clock (to the bottom-left FF).

But you are completely ignoring the set-up and hold time requirements. In this case, your bottom counter is trying to go from 1100 to 0010 (as drawn, which is lsb on the left) but the logic signal from your AND gate is very brief. Not only is it violating any positive set-up time on that first FF, but by the time the output of the first FF gets to the third, your AND gate output has gone back LO, meaning that the last third FF doesn't toggle.

Unless you are willing (and capable) of properly vetting an asynchronous design (something that very few students at this point are in a position to do), you need to design your logic so that it is fully synchronous.

 

I know that. I want to reset after reach the 60 sec but it got reset at 40 sec without need R input.

You do not have a valid input voltage on the R inputs.
Connect the inputs to Vcc or GND, whichever is needed to NOT reset the flip-flops.

 

You do not have a valid input voltage on the R inputs.
Connect the inputs to Vcc or GND, whichever is needed to NOT reset the flip-flops.

While I absolutely agree, I'm guessing that this is only being done in simulation and many logic simulators assume that undriven inputs are at GND (which I personally think is not wise, but they do this in the name of stacking the deck in favor of being able to simulate circuits -- though some do it because they are ultra-simplistic and every node only allows for LO or HI).

If it is being done in sim-only, the behavior he is seeing is not due to the floating reset inputs, since the simulator almost certainly has no concept of noise on high-impedance nodes. I strongly expect that the problem is set-up/hold time violations.

 

While I absolutely agree, I'm guessing that this is only being done in simulation and many logic simulators assume that undriven inputs are at GND (which I personally think is not wise, but they do this in the name of stacking the deck in favor of being able to simulate circuits -- though some do it because they are ultra-simplistic and every node only allows for LO or HI).

If it is being done in sim-only, the behavior he is seeing is not due to the floating reset inputs, since the simulator almost certainly has no concept of noise on high-impedance nodes. I strongly expect that the problem is set-up/hold time violations.

TS did not state if the behavior observed was on a simulator or a real circuit.
I am making an assumption that it was on a real circuit. I cannot find a reason for the simulator to give the stated result.

 

TS did not state if the behavior observed was on a simulator or a real circuit.
I am making an assumption that it was on a real circuit. I cannot find a reason for the simulator to give the stated result.

I explained exactly how the stated result could come about. But let me be even more explicit.

The exact details of the behavior depend on specifics of how the simulator (or the real circuits) deal with set-up and hold time requirements, so there is a small range of possibilities. The main possibilities for the bottom counter is to never change at all, to go from 1 to 0, to go from 3 to 0, and to go from 7 to 0. The TS is observing the case of going from 3 to 0.

The fact that the left-hand DFF is changing at all, when the J, the K, and the CLK inputs are all driven by the same signal, indicates that the set-up time is zero, which is a common characteristic of simple simulators (or simulation models). For a simulator to work at all with feedback sequential circuits, there has to be some notion of propagation delay, at least for sequential logic elements, from CLK to output as well as some notion of hold time at the data inputs relative to the clock. Furthermore, the hold time has to be less than the propagation delay, otherwise an output of a register fed back to an input would cause oscillating. There are a couple ways to implement this notion, but it has to be there. While there doesn't necessarily have to be a notion of propagation delay through combinatorial elements, there usually is, since it is pretty much free if you have to already deal with it for sequential elements.

So let's say that the propagation delay from Clock or R to Q for a FF is 5 units and that the propagation delay through a gate is 1 unit.

What happens when the top set of FF get to 0101 (as seen in the schematic, but 10 in decimal since the lsb is on the left)? Let's say that the right-most FF's Q output goes HI at t=0.

At t = 1 unit, the AND gate output goes HI. This asserts the R input to all of the top FFs and, 5 units later, at t = 6 units, all of the Q outputs go LO and at t = 7 units, the output of the AND gate goes LO.

This means that the J and K inputs to ALL of the bottom FFs is HI from t = 1 unit to t = 7 units and LO otherwise.

Now let's say that the bottom FFs are currently in state 1100 (3 in decimal, remember, lsb is on the left)

The CLK input of the left one goes HI at t = 1 units. With zero set-up time, the FF will see the J and K inputs as HI and will toggle the output from HI to LO at t = 6 units, which is also when the Qbar output goes LO to HI, taking the CLK input of the second FF HI at t = 6 units.

When the second FF is clocked at t = 6 units, it's J and K inputs are still HI, so it toggles and both of it's outputs change at t = 11 units.

However, when the third FF is clocked at t = 11 units, what are its J and K inputs? They are LO, because the output of the AND gate went LO at t = 7 units. So the third FF, whose output is already LO, stays the same. The fourth FF never gets a CLK pulse, so it does nothing and stays LO.

You can change these over a pretty wide range and still get similar behavior, what really drives the specific behavior seen is having the CLK to Q and the R to Q delays being the same or similar, which is pretty common in simple FF models. Thus, the most likely behavior is for the system to count up to 39 and then go back to 00, just as the TS is seeing.

These relationships are also pretty similar for actual FF's, so it would not be surprising to see the same behavior in a physical circuit, although the chances of it varying one way or the other are quite a bit higher, especially given parameter variations from one FF to another.

 

Thank you everyone for helping me. I done the digital clock but not an alarm I have no idea how to make an alarm work. Can someone help me with that. This is my clock.

 

You are using a lot of gated clocks -- that's a recipe for disaster unless you thoroughly vet your design to establish that those clocks are guaranteed to be glitch free over all spec'ed parameters of the devices.

Have you done that?

As for the alarm, what kind of alarm do you need?

 

You are using a lot of gated clocks -- that's a recipe for disaster unless you thoroughly vet your design to establish that those clocks are guaranteed to be glitch free over all spec'ed parameters of the devices.

Have you done that?

As for the alarm, what kind of alarm do you need?

Yes, I know it would be disaster if it goes wrong. But my course only teaches me the basic so I can't use any kind of advanced circuits for assignment.


For an alarm I have done it, but I have a glitch that I don't understand why. My design is using another counter that don't use the clock the only method to change that clock is increase by hand. Then compare 2 counters (the digital clock and the alarm counter) if it equals it will send a signal to store 1 bit in the D flip flop and stay there until I turn off the alarm by myself. But problem is, sometime the flip flop trigger and store 1 bit inside without a signal from the compare. Can you help me to find the problem. This is my file, using Logisim-evolution app to open.

In this case, I set an alarm at 01:00 and the alarm trigger at 01:00. But when I turn it off, it continues to trigger at 01:02, 01:04, 01:20, 01:40 without need a signal from the compare.

https://drive.google.com/file/d/1QurEltCRQBN7cZSgqHPzvpXYia8GBBqA/view?usp=sharing

 

After a week I finally did it. It's a bit messy but I think it worked fine. Thank you everyone that help me to understand the synchronous circuit. It's hard to understand that because the simulator didn't show it properly. The only way to test it is using D flip flop that have trigger condition at High level. But after all, I fixed all my issue.