Do Spice Models for MOSFET include lead inductance?
In specific, the LTSpice VDMOS models?
If not, will the circuit behavior be different from what it acually is?
I read this IR application note, but not clear still.
www.irf.com/technical-info/appnotes/an-1194.pdf

 

Hi,

I would say it would be dependent on the model itself, some might include it some might not, so you have to know how to find out from the model itself not from a blanket policy.

As you probably know, the lead inductance is important when trying to determine how much the circuit might ring. Especially the source inductance, which causes gate feedback and therefore can mess up the switching of the MOSFET pretty badly sometimes. Normally the thing to pay most attention to though is the external wiring, such as that to the source, which would probably swamp the internal inductance. For closely spaced MOSFETs however the internal lead inductance might come into play. All of the circuits i ever did in the past had more external lead inductance than internal, so the circuit mostly depended on that not the internal part.

 

(just a guess): One quick way to tell if check if the package is specified, assuming multiple package types.

As each package would have a different lead inductance each would have a different model if that is part of the model.

However, as MrAl puts it, your external circuit will be the dominant source of inductance.

 

Thanks MrAI & ErnieM.
I was trying to simulate a synchronous buck converter and measuring the rise time of current. It was always too fast to give undershoot at the switch node with practical parasitic inductance.
I tried putting 7nH & 15nH on the Drain & Source IRFP4668 respecively and simulated it in LTSpice to find decent results. MrAIs source inductance messing with gate explanation is nice. ErnieM, that is a good idea to experiment from packages!