Hello!
I have done calculations for designing a differential amplifier (DA) with differential output. I simulate (using cadence ) the DA with the calculated values and perform the DC analysis of the circuit to inquire all the transistors are operating in saturation. However, I did not get all the transistors in the saturation region. I tried to tune the system (means to bring it to saturation region) but tuning one set of transistor results in the detuning of other transistors and vice versa.

if someone can review my calculations and suggest me correction. I will be thanked for my help.

Design Parameters:

GBW= 5MHz CL= 10pF, Vdd=5V

UnCox=151u A/V^2;

UpCox=26u A/V^2;

Av= 100

Vtn=0.85V Vtp=-1V

Slew Rate (SR) :5V/uSec

ICMR+= 4V ; ICMR- =1.5V (input Common mode range)

Step 1 _ Calculating Id:

Id=SR*CL 5V/uSec * 10pF= 50uA

Step 2 - Calculating (W/L) for M3 and M4:

Vds1>=Vmax-Vthn=4-0.85=3.15V (let consider it as 3.5V)

Vds3=Vdd-Vds1=5-3.5=1.5V

For M3 to be in saturation:

|Vds3|>=|Vgs3|-|Vthp|

1.5V >= |Vgs3| - 1V

|Vgs3|<= 2.5V (I take |Vgs3| : 2V )

Id3=Id/2 = 25uA

(W/L)3= 2* Id3 / UpCox * (|vgs3| - |Vthp| = 2

Step 3 - Calculating (W/L) for M1 and M2:

gm1=GBW * 2 * pi * CL

= 5M * 2 * 3.14 * 10pF

=314u

Id1=Id/2=25uA

(W/L)=gm1^2 / 2 * Id1 * unCox

(W/L) =13.06

Step 4 _ Calculating (W/L) for M5 and M6:

To keep M1 in saturation under ICMR- (1.5V):

Vin>=Vgs1+Vdsat5

Vgs1=1V (I calculate it as we know Id1=25uA , W1/L1=13.06 )

Putting Vin=1.5 (ICMR-) & Vgs1= 1V

Vdsat5<=0.5V

Id5=Id

(W/L) =2 * Id5 / UnCox * (Vdsat) ^ 2= 2.64

Finally, transistor dimensions are:

(W/L)1,2 = 1.9u / 1u

(W/L)3,4 = 13.06u / 1u

(W/L)5,6 = 2.64u / 1u

 

Are all your FETs the same? Can't tell from the schematic...

And why do you want them in saturation?

 

Is this a Classroom-Assignment ?
Why don't you just buy one, they're less than ~5-Bucks.
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.
.

 

Is this a Classroom-Assignment ?
Why don't you just buy one, they're less than ~5-Bucks.
.
.
.

This is not a class assignment. Actually, my ultimate goal is to design a Fully Differential Amplifier. The first step is a differential amplifier with differential output, then CMFB design.

 

Are all your FETs the same? Can't tell from the schematic...

And why do you want them in saturation?

Thanks for your response. I make a mistake in drawing the schematics. Actually, the FETs M3 & M4 are pmos while the rest are nmos. My ultimate goal is to design a Fully Differential Amplifier. The first step is a differential amplifier with differential output, then CMFB design.
In a differential amplifier with differential output, all the FET's should be in saturation.

 

I don't believe this isn't a homework assignment!
See

 

In a differential amplifier with differential output, all the FET's should be in saturation.

True, but that's not really the answer to my question, which was checking your understanding of what saturation means and its relevance in this context....

i was going to post my simulation., but @Bordodynov has posted a similar one...

 

I don't believe this isn't a homework assignment!
See
View attachment 241576

Thanks, @Bordodynov, and @Irving for the simulation and suggestion. It helped me to address my issue and got my diff amp with diff output.
Once again to mention: It's not a class assignment

 

Thanks, @Bordodynov, and @Irving for the simulation and suggestion. It helped me to address my issue and got my diff amp with diff output.
Once again to mention: It's not a class assignment

So whats the end goal in this ,

Are you doing all this in simulation
or is the aim to make one out of discrete parts
or even on a chip ?

 

So whats the end goal in this ,

Are you doing all this in simulation
or is the aim to make one out of discrete parts
or even on a chip ?

@andrewmm
This is one of the discrete part of the system. The aim is: demodulating the differential signal which is part of the on-chip isolated transmission system using the capacitive coupling technique, for that, I am initially doing simulations in the cadence tool.

I am designing a fully differential amplifier, which includes: Differential amplifier (with differential output ), CM detector, and CMFB loop. The first task is done, now I am moving to the CM detector design and then the CMFB loop. Ultimately I need to design the entire system on a chip.

 

Just to clarify , this is on chip design, not individual parts wired together, your designing a chip,
I'm guessing for end of year at university ?

what foundry models are you using ?

 

Just to clarify , this is on chip design, not individual parts wired together, your designing a chip,
I'm guessing for end of year at university ?

what foundry models are you using ?

This is an on-chip design, not a wired one. I am using AMS 0.35um technology.

 

Wow

Fantastic,

I ask as the advice we could give you is probably mainly centred around separate chip / resistor designs,
a chip fab is a bit different, You can do a lot of different things on chip that you can't with external parts,