I know ceramic caps are cheap and that you guy's all say one for each chip, but the TTL and CMOS cookbooks recommend one cap for every six chips. Is there a reason why there is such a discrepancy?

Maybe I'm the person who's least qualified here to answer that question properly. But I'm guessing that not all scenarios are equal. My specific case, for instance, is a little extreme.
Plus, the distance between the cap and the chip is very important. Maybe that's why people here generally recommend one cap per chip.

 

Connect the choke between the 12VDC source and the input to your 120V switcher, and your filter cap between the switcher input and ground. 1000μF should be more than enough...

What if I were to add one of these suckers in line to the Vcc pin of each chip?

 

I have a 36V, 1KA pulse gen under common ground 5V PIC control running on my workbench. These capacitive pulses can occasionally cause arcing/welding when there is a weak connection. Pulse currents heat up the 1' long, 4 x 12AWG copper cabling to 50°C. The PIC (16F886) never resets. The PIC does ADC sampling of pulse voltages and currents.

It employs two levels of linear regulation (12V & 5V) using LM317 lower noise regulators (spec sheet schematics). I use a healthy sprinkling of 500mA, Type R ferrite beads. http://www.farnell.com/datasheets/714910.pdf on the ADC lines.

Hall effect linear current sensors are employed for isolation. Voltage sensing is done via an LM324 jelly bean OPA configured as a diff amp operating as a class A and using a 1/4 voltage divider input made up of 133K x 4 resistors which have a 18V Zener clamp midway in the resistor chain.
Opto isolation is employed to drive the FET bank via a 6A MCP1407 gate driver (12V). The gate driver decoupling has a 0.1uF, a 1uF, a 10uF X7R and a 100uF electrolytic. The 100uF makes a significant difference in the gate pulse as the 12V supply run is long @ 3".

X7R 0.1 uf decoupling caps are standard, .01uf /1kohm RC decoupling added to the ADC lines as there are flying ADC leads picking up significant pulse EMI. uC proximity to the high current pulse cables is about 4" . Pulse ringing is about 5Mhz primary harmonic. Kickback energy from cabling inductance requires heavy duty snubbing. Around 40A for 10uSec must be controlled. But even without snubbing the kickback & ringing do not reset the uC or affect the ADC readings. I have melted/popped many TVS, rectified RC snubbing was required.

Ground plane design isolates high current sections from the logic to create analog/digital type grounding. High current sections are augmented with solder braid to reduce impedance driven voltage bounce.


In summary:
Low impedance ground plane design with isolated paths for analog and digital currents.
Wide bandwidth ferrite beads on exposed signal lines.
Decoupling capacitors (SMT ideally) across Vcc/Gnd at each IC, including RC filter on signal lines where possible.
Galvanic isolation e.g. via hall or opto.
Low ESR Electrolytic (10uF +) decoupling of Vcc/Gnd at wire to board junctions if you have multiple PCBs.
Twisted pair sensor wiring (e.g. Kelvin voltage sampling) where possible with ferrite beads at PCB input traces.
Proper termination of unused I.C. pins, including analog pins in spare op amps.
Do NOT place ferrite beads in the post regulator power rail. Never place them in the ground return.

PS: in this app the µC also samples the pulse widths generated by a TL494 via the µC T0CK and T1G pulse timing hardware (around 9µS to 300µS, 2000µS period) and does its ADC oversampling 'between' the pulse events with additional timing clearance (10µS) to avoid the ringing impacting the ADC values.

 

I know ceramic caps are cheap and that you guy's all say one for each chip, but the TTL and CMOS cookbooks recommend one cap for every six chips. Is there a reason why there is such a discrepancy?

Speaking for myself, I think it's just an abundance of caution: in my experience over the years (I started in 1965), I've found that glitches due to power and ground distribution screwups (inadequate decoupling caps, incorrect ground topography, etc.) have been the most horrendous to diagnose. So my default setting is to deal with them in a brute-force fashion.

 

What if I were to add one of these suckers in line to the Vcc pin of each chip?

Nah. That simply unnecessary, gross overkill.

 

What if I were to add one of these suckers in line to the Vcc pin of each chip?

1.1Ω DC-R will cause significant supply rail bounce/noise dependant on the switching load of the digital device. Depending on the current requirements of the digital part that solution introduces its own set of problems.

 

Speaking for myself, I think it's just an abundance of caution: in my experience over the years (I started in 1965), I've found that glitches due to power and ground distribution screwups (inadequate decoupling caps, incorrect ground topography, etc.) have been the most horrendous to diagnose. So my default setting is to deal with them in a brute-force fashion.

Brute-force is sometimes my first approach... and if that doesn't work, then I'll try to reason my way out of trouble...