Hi,
I'm designing a PCB (8x4 inch) with a micro-controller and some Op-amps and relays etc.
Have some questions in mind about small value decoupling/bypass capacitors (PFs) used in PCBs. I know these capacitors are low value (About 0.1uF) and absorb high frequency ripples from power supply because large filter capacitors can't do this and these needs to be placed as close close as possible to IC power supply pins etc.
Some questions in my mind are,
1. If an IC has more than two power supply pins (e.g PIC16F946 has 4 VDD and 4 VSS pins). Should these capacitors be placed at each pair of supply pins?
2. Should these be placed only at P.S pins or can be placed all around power supply path? Means if tracks from filter capacitor to IC pins are long path.
3. What are the optimized places where these capacitors should be placed. Is there any quantity recommendation?
Power supply is an external 12V SMPS and then a 7805 Regulator on board. System would be used in a noisy industrial environment.
(Sorry if my English is non standard)
Thanks and best regards.

 

Yes, on every physically (with a gap of at least one pin) isolated power pin.

A pretty good note on the subject. There are bypass and decoupling requirements.

https://www.renesas.com/us/en/document/apn/an1325-choosing-and-using-bypass-capacitors

https://resources.altium.com/p/bypass-and-decoupling-capacitor-placement-guidelines

Power integrity problems are normally viewed from the perspective of the power supply, but looking at the output from ICs is just as important. Decoupling and bypass capacitors are intended to compensate for power fluctuations seen on the PDN, which ensures your signal levels are consistent and a constant voltage is seen at the power/ground pins on an IC.

Decoupling and bypass capacitors are used to solve two different power integrity problems. Although these power integrity problems are related, they manifest themselves in different ways. The first point to note is that the terms “decoupling capacitor” and “bypass capacitors” when used for power integrity are misnomers; they don’t decouple or bypass anything. They also do not pass “noise” to the ground; they simply charge and discharge over time to compensate for noise fluctuations. These terms refer to the functions of these capacitors as part of a power integrity strategy.

 

It's not that complicated, as short, direct and thick as practical. For a controller the placement of the caps is usually not super critical.
A PCB design tip I often ignore but is good design. For the bypass and decoupling caps don't use thermal pads on GND/VSS pads on ground pours to reduce series inductance. The caps store the electrical energy from the noise sources, making all paths as close to zero impedance is something you should think about.

Think about where water would pool and flow if the traces and copper were indentations on a solid surface, narrow channels on the surface can cause turbulences due to 'resistance', you want wide channels like the Mississippi river.

A simple example of a 99% auto routed (room for improvement) 4 layer board designed for high EMI environments:



Image with the board substrate and devices removed to show top and bottom ground polygons.

 

1. If an IC has more than two power supply pins (e.g PIC16F946 has 4 VDD and 4 VSS pins). Should these capacitors be placed at each pair of supply pins?

The rule of thumb is to put a decoupling cap on each power pin.

2. Should these be placed only at P.S pins or can be placed all around power supply path? Means if tracks from filter capacitor to IC pins are long path.

It depends on the design of your power network and the calculations aren't necessarily straightforward.

3. What are the optimized places where these capacitors should be placed. Is there any quantity recommendation?

A conservative approach is one cap per power pin. For higher frequencies, smaller caps are placed in parallel with the typical 0.1uF caps. Ground lead/trace length should be short minimize inductance (that's why electrolytic caps don't work well at higher frequencies).

The attached PDF discusses power grid design for a static memory board on page 7, decoupling is discussed on page 8. Note that Intel did not recommend putting decoupling caps on each IC power pin and suggested using tantalum reservoir caps distributed on the power grid.

Having mechanical relays on the board will complicate things. I had one where I couldn't eliminate glitching caused by the relay switching.

 

@nsaspook , @dl324
Thanks a lot for such useful tips and stuff.
Mechanical relays are a must part of my PCB. They are using a separate PS rail rather than 5V. Before, in my PCB, I've used relays in this fashion and a freewheeling diode did the job just fine with a good GND plan.
Again thanks for your valuable help.
Best regards.