Hello,

I do a simulation on the attached schematic. The input is 12-0V square wave with 50% duty cycle at f=8kHz. I want to know the Q1's collector current waveform, so I connect R3 = 1 ohm, and measure the voltage across it. As you can see, when the input is 12V, V+ - V- = 450mV. This means there is a current from the left pin of R3 to the right pin.

My question:
When Vin =12V, does this mean the current of Q1 flow from emitter to collector? If so, why does the NPN transistor carry such a current?

Thank You
BlackMelon

 

When Vin =12V, does this mean the current of Q1 flow from emitter to collector?

No. It means current flows through the base-collector junction, which is forward-biased.

 

See

 

No. It means current flows through the base-collector junction, which is forward-biased.

Does that mean Q1 is in a deep saturation? (Vb >>Vc and Vb>>e)? So, what exactly is the direction of Ic and Ie of Q1?

See
View attachment 130449

Try the one in the attachment. No more Vbe overvoltage. The Q1 is in saturation, so we don't have the full advantage of beta^2 here. I just want to see how Darlington's pair behave in the saturation region. (waveform of currents, voltages, etc.)

 

I wanted to show you the error. Putting into the base of the transistor 10 Ohm, you raped a transistor. The maximum power of the transistor is ~ 2.5 W, Average 1.25 W. In reality, the transistor will emit smoke. I recommend putting in base 10 kOhm.

 

I do not intend derail this thread but, isn't a Darlington pair like the one below? Please note that the TS/OP used the name in the image attached to the OP.

The many I implemented no one had any load in the collector.

Intrigued.

 

Does that mean Q1 is in a deep saturation? (Vb >>Vc and Vb>>e)? So, what exactly is the direction of Ic and Ie of Q1?

Yes. Ic is out of the collector. Ie is out of the emitter.

 

I wanted to show you the error. Putting into the base of the transistor 10 Ohm, you raped a transistor. The maximum power of the transistor is ~ 2.5 W, Average 1.25 W. In reality, the transistor will emit smoke. I recommend putting in base 10 kOhm.

Yes, thank you for your warning. In my new schematic, I have corrected that problem. May be 50kohm is too high? The purpose of this simulation is to see how Darlington pair behaves when it enters saturation region.

I do not intend derail this thread but, isn't a Darlington pair like the one below? Please note that the TS/OP used the name in the image attached to the OP.

The many I implemented no one had any load in the collector.

Intrigued.

Of course, you are correct. But adding 1ohm resistor between both collectors will not change the behavior of the circuit much. It's so low that in practical it can be considered as a resistance of a copper wire. Some current sensing uses this technique too.

Yes. Ic is out of the collector. Ie is out of the emitter.

Thank you again. So, the max current Itot(max) is less than the Ic2(max)? (From the schematic, Itot(max) = Ic2(max) - Ic1). We have more current gain, but less maximum current?

 

Hello,

I do a simulation on the attached schematic. The input is 12-0V square wave with 50% duty cycle at f=8kHz. I want to know the Q1's collector current waveform, so I connect R3 = 1 ohm, and measure the voltage across it. As you can see, when the input is 12V, V+ - V- = 450mV. This means there is a current from the left pin of R3 to the right pin.

My question:
When Vin =12V, does this mean the current of Q1 flow from emitter to collector? If so, why does the NPN transistor carry such a current?

Thank You
BlackMelon

Before you do a simulation, do a quick sanity check to see how you expect the circuit to behave with very simple component models. Don't fall in love with the simulator so much that you let it do your thinking for you -- YOU are designing the circuit, not the simulator. So YOU need to at least be able to estimate the gross behavior that makes sense.


If Vbe is about 0.7 V, then the base of Q1 is going to be at 1.4 V.

When V1 is at 12 V, that means that the voltage across R1 is going to be 10.6 V and so right about 1 A of current is going to flow.

With R2 sized the way it is, the current through it can't exceed 12 mA, so this means that Q1 and Q2 are going to be in serious saturation.

Let's assume that the saturation voltage is 0.2 V. That means that the collector of Q2 will be at about 0.2 V while the collector of Q1 will be at about 0.9 V, so you have about 0.7 V across R3 in such a way that about 700 mA of current will flow OUT of the collector of Q1 and down into the collector of Q2. The rest of the base current in Q1, or about 360 mA, will flow out the emitter and into the base of Q2. The current in R2 will be just under 12 mA, and be completely dwarfed by the other currents.

Now, keep in mind that this is just a very, very rough walkthrough of the circuit with a very simple model for the transistors. With that much base current, the actual Vbe is going to be quite a bit higher. Also, the Vbe when both the base-emitter and base-collector junctions are strongly forward biased doesn't follow the simply models well at all.

 

Of course, you are correct. But adding 1ohm resistor between both collectors will not change the behavior of the circuit much. It's so low that in practical it can be considered as a resistance of a copper wire. Some current sensing uses this technique

Well, no. I was thinking of the 1K resistor.

 

The collector current of the first transistor can be positive, negative and zero. It depends on the resistor in the base. The figure shows this current for resistors of 1 kΩ and 200 kΩ. Also, the value of the resistor at zero collector current of the first transistor is calculated.
See