# Book Example for Differential Amplifier with Darlington Doesn't make Much Sense

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
I have been trying to understand some of the examples in the chapter for over 2 weeks now, and so much isn't adding up. The book often doesn't explain their use of labels or subscripts and often leaves me scratching my head, guessing on what the precise intended meaning is. This text also tends to just throw numbers into a calculation without citing the variables in the equation/formula used. I can sometimes come up with a pretty good guess what they might be talking about, but occasionally I am completely at a loss on why the numbers used are present. The question I am looking at is Example 9.4 in the Chapter 9: Practical Operational Amplifiers of the Textbook Electronic Design: From Concept to Reality. It's worth noting that I had the prerequisite material for this course using Microelectronics by Sedra & Smith back in 2018 which used some different notation in some cases. I'm picking up on the followup course at a different school, using a different text. Anyways the questions are written on my photocopies in red. Some questions I have better ideas what the answers may be than others, so its not like I am completely clueless.

#### WBahn

Joined Mar 31, 2012
30,236
Based on what you are showing here, this looks like a pretty poor textbook, so I can see why you are having problems.

Let's tackle one thing at a time, so let's look at the current source.

You seem to be having trouble with determining the voltage across R1 and matching that up to the author's numerator in Section 3.

So what is the voltage on the left-hand side of R1? It's 0 V.

What is the voltage on the right-hand side of R1? It's 0.6 V above Vee, which is -12 V. So it's (-12 V + 0.6 V).

The voltage across R1 is then simply the voltage on the left side minus the voltage on the right side:

V_R1 = (0 V) - (-12 V + 0.6 V) = 12 V - 0.6 V

Don't hesitate to fall back on basic circuit analysis.

#### LvW

Joined Jun 13, 2013
1,765
Answer to one of your questions (2nd expression below the diagram on the most left side):

The quantity "re" is not an "emitter resistance" - it is a symbol for the inverse transconductance (re=1/gm).
Therefore, it (a) does not belong to the emitter portion of the device and (b) it is not a resistance at all.

I have often experienced that this way of taking the transconductance gm in a formula into account has led to misunderstandings.

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
Based on what you are showing here, this looks like a pretty poor textbook, so I can see why you are having problems.

Let's tackle one thing at a time, so let's look at the current source.

You seem to be having trouble with determining the voltage across R1 and matching that up to the author's numerator in Section 3.

So what is the voltage on the left-hand side of R1? It's 0 V.

What is the voltage on the right-hand side of R1? It's 0.6 V above Vee, which is -12 V. So it's (-12 V + 0.6 V).

The voltage across R1 is then simply the voltage on the left side minus the voltage on the right side:

V_R1 = (0 V) - (-12 V + 0.6 V) = 12 V - 0.6 V

Don't hesitate to fall back on basic circuit analysis.
WOW!!! Thank you, that was quite helpful, and explained VERY clearly. If the author would have consistentlyt written the text like how you just illustrated and explained this calculation, they would be drastically more clarity!

I see a calculation for something called "Ic". Some evidence (particularly the 400 ohm and 4k-ohm resistors connected to Q6 adding up to 4400 ohms) points to it possibly being related to Q6. However, the calculation seems to suggest that there is also a 4000 ohm resistance in series with 4400 ohms, which I don't see on the diagram.

Other evidence (namely resistor with the label "Rc" occur on Q1 and Q2). I don't have much faith in the text keeping labeling conventions consistent, but if it were up to me me, I would define and label Ic as the current which runs through Rc, which has voltage drop Vc across it. aka so that Ic = Vc/Rc). The resistor values used in calculation of the current seem to suggest that its probably Q6, but not everything is adding up clearly.

#### WBahn

Joined Mar 31, 2012
30,236
You are actually observing something that I am always harping on students (and practicing engineers) about. So take the resulting lessons to heart. When you present your work, be sure to clearly and unambiguously define your terms. For instance, instead of just throwing some numbers in an equation for R1, it should have been something like R1 = V_R1/I_C4 and then V_R1 and I_C4 should have been clearly annotated on the diagram, including polarity.

Also, this author (like, sadly, most authors, including Sedra and Smith, despite how good their book is overall) refuses to properly track units. Instead, they throw a bunch of unitless numbers around and then tack some units onto the final result based on what they hope/expect the units to be. That's extremely sloppy, no matter how commonplace.

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
Answer to one of your questions (2nd expression below the diagram on the most left side):

The quantity "re" is not an "emitter resistance" - it is a symbol for the inverse transconductance (re=1/gm).
Therefore, it (a) does not belong to the emitter portion of the device and (b) it is not a resistance at all.

I have often experienced that this way of taking the transconductance gm in a formula into account has led to misunderstandings.
Thank you Lvw, this was an important point to clear up!

So if I understand correctly, re = VT/Ic, where VT is the thermal voltage, KT/q = 26 mV approximately (depending on whatever T is), and Ic is the current running through the collector of the particular transistor in question then?

I am more familiar with gm than re from my electronics class back in 2018. I kind of remember using gm to make dependent sources in the small signal model, and that we were told that conductances were easier to work with than a resistance in the model.

Speaking of signal models, one concept I recall is treating large signal models (DC) and small signal models separately, and the overall outputs can be represented by summing the results of small signal and large signal analysis together.

For the purposes of this problem, I think only the small signal model is necessary here since common mode gain and differential mode gains are small signals, right?

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
You are actually observing something that I am always harping on students (and practicing engineers) about. So take the resulting lessons to heart. When you present your work, be sure to clearly and unambiguously define your terms. For instance, instead of just throwing some numbers in an equation for R1, it should have been something like R1 = V_R1/I_C4 and then V_R1 and I_C4 should have been clearly annotated on the diagram, including polarity.

Also, this author (like, sadly, most authors, including Sedra and Smith, despite how good their book is overall) refuses to properly track units. Instead, they throw a bunch of unitless numbers around and then tack some units onto the final result based on what they hope/expect the units to be. That's extremely sloppy, no matter how commonplace.
Amen to this, I agree 100%; and, I will take that as a compliment! This flaw has probably multiplied my time spent on this course by a factor of 3! If I recall correctly, one example of a textbook that was usually being decent about labels and polarity markings is Alexander & Sadiku's Fundamentals of Electric Circuits It's not a flawless text, but Alexander & Sadiku's book is among my favorites because they always have practice problems immediately following the example problems that utilize the exact same tricks and techniques as the preceding example.

I am understanding your blurb about I_C4 and V_R1 to be an arbitrary example illustrating how to use labels clearly, but not specific to any reference designators used in this particular problem, if I'm following you correctly.
Speaking of ambiguous labels. The problem statement says V_A = 80V. Do you have any idea where the 80V V_A should appear on the diagram?
I see that 80V is used later on to calculate the Thevenin equivalent of something, but I don't know what it is the thevenin equivalent of. It's just called "R_TH."
Anyways would you be able to tell me why 4000 is added to 4400 (assuming this is indeed Q6 afterall)?

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#### WBahn

Joined Mar 31, 2012
30,236
I see a calculation for something called "Ic". Some evidence (particularly the 400 ohm and 4k-ohm resistors connected to Q6 adding up to 4400 ohms) points to it possibly being related to Q6. However, the calculation seems to suggest that there is also a 4000 ohm resistance in series with 4400 ohms, which I don't see on the diagram.
The author's work in Section 1 is, indeed, poorly presented and is like pulling a rabbit out of a hat. It's impossible to tell what assumptions and simplifications they are making, so the values they use have a certain "magical" flavor to them.

Let's call the 4 kΩ resistor Rc and the 400 Ω resistor Re. Let's then define Ic to the the current flowing downward through Rc.

The first assumption we will make is that whatever current is flowing in Rc is the same current that is flowing in Re. This is a pretty good assumption since the difference is just the base current in Q5, which is a negligible fraction of Ic.

What we need to determine is what the DC bias value of Ic needs to be in order to allow maximum output signal swing of the output.

The output voltage is simply

Vout = Vcc - Ic·Rc

The maximum Vout is when Ic = 0, which means

Vout_max = Vcc.

The minimum Vout is when the transistors drop out of the active region and move into saturation. Here is where we need to make some additional assumptions. For simplicity, we can consider this to happen when Vce for Q6 = 0 V, which means that

Vout_min = Vcc(Re/(Re+Rc))

So the quiescent Ic is the current that corresponds to Vout being midway between Vout_min and Vout_max.

Of course, we know that we can't get Vce of Q6 down to 0 V. A better estimate would be Vce_Q6 = Vbe_Q6 + Vce_Q5, The value of Vce_Q5 to use is open for discussion, but using Vce = 2·Vbe is not unreasonable.

If we use Vce_Q6 = 0 V and do the analysis (assuming I didn't make any mistakes as I did it quickly), you end up with

Ic = Vcc / [2(Rc + Re)]

It wouldn't surprise me if a different assumption regarding Vce_Q6 results in Vcc / (2Rc + Re), which is what the author appears to have.

#### WBahn

Joined Mar 31, 2012
30,236
Amen to this, I agree 100%; and, I will take that as a compliment! This flaw has probably multiplied my time spent on this course by a factor of 3! If I recall correctly, one example of a textbook that was usually being decent about labels and polarity markings is Alexander & Sadiku's Fundamentals of Electric Circuits It's not a flawless text, but Alexander & Sadiku's book is among my favorites because they always have practice problems immediately following the example problems that utilize the exact same tricks and techniques as the preceding example.

I am understanding your blurb about I_C4 and V_R1 to be an arbitrary example illustrating how to use labels clearly, but not specific to any reference designators used in this particular problem, if I'm following you correctly.
Speaking of ambiguous labels. The problem statement says V_A = 80V. Do you have any idea where the 80V V_A should appear on the diagram?
I see that 80V is used later on to calculate the Thevenin equivalent of something, but I don't know what it is the thevenin equivalent of. It's just called "R_TH."
Anyways would you be able to tell me why 4000 is added to 4400 (assuming this is indeed Q6 afterall)?
V_A is the Early voltage of the transistors and plays the dominant role in determining the small-signal output resistance off the transistor.

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
The author's work in Section 1 is, indeed, poorly presented and is like pulling a rabbit out of a hat. It's impossible to tell what assumptions and simplifications they are making, so the values they use have a certain "magical" flavor to them.

Let's call the 4 kΩ resistor Rc and the 400 Ω resistor Re. Let's then define Ic to the the current flowing downward through Rc.

The first assumption we will make is that whatever current is flowing in Rc is the same current that is flowing in Re. This is a pretty good assumption since the difference is just the base current in Q5, which is a negligible fraction of Ic.

What we need to determine is what the DC bias value of Ic needs to be in order to allow maximum output signal swing of the output.

The output voltage is simply

Vout = Vcc - Ic·Rc

The maximum Vout is when Ic = 0, which means

Vout_max = Vcc.

The minimum Vout is when the transistors drop out of the active region and move into saturation. Here is where we need to make some additional assumptions. For simplicity, we can consider this to happen when Vce for Q6 = 0 V, which means that

Vout_min = Vcc(Re/(Re+Rc))

So the quiescent Ic is the current that corresponds to Vout being midway between Vout_min and Vout_max.

Of course, we know that we can't get Vce of Q6 down to 0 V. A better estimate would be Vce_Q6 = Vbe_Q6 + Vce_Q5, The value of Vce_Q5 to use is open for discussion, but using Vce = 2·Vbe is not unreasonable.

If we use Vce_Q6 = 0 V and do the analysis (assuming I didn't make any mistakes as I did it quickly), you end up with

Ic = Vcc / [2(Rc + Re)]

It wouldn't surprise me if a different assumption regarding Vce_Q6 results in Vcc / (2Rc + Re), which is what the author appears to have.
Dude, do you have a Paypal or a Venmo? Your explanations are AMAZING! I'm getting answers to questions that I have spent HOURS and HOURS on trying to puzzle through on just this one example, and all the pieces of this puzzle are coming together so clearly at breakneck speed thanks to your help! And yes, reading the analysis from the author did indeed feel like numbers were pulled magically out of hat! That's exactly what it felt like!

If I am understanding this properly, Q5 is NOT in saturation, but only Q6 is in saturation during the case where Vout in minimum?

#### WBahn

Joined Mar 31, 2012
30,236
Actually, Q5 can go into saturation but Q6 won't. That's because if Q6 is in saturation, that would require Vce for Q5 to be negative.

But that's a pretty minor point and has little impact on the operation of the amplifier, since if ANY of the transistors go into saturation we are pretty much guaranteed that the amplifier as a whole is not behaving as it should.

In practice, we don't want to let Vout get too near Vcc or the minimum voltage, because in doing so we will likely have moved well outside the range of operation where we have good performance (e.g., low distortion). But those two theoretical operating points are useful because it allows us to park the quiescent operating point midway between them which gives us the best chance of obtaining the largest output voltage swing about that point that has acceptable performance. We probably won't have the actual optimum operating point, but we are probably close enough.

Another way to come up with the same result that I had before is to find the maximum possible current in Rc and set the quiescent current to half of that, which will park Vout in the middle of its output range.

Let's call the minimum collector-emitter voltage of Q6 Vce_min. Again assuming that Ic = Ie, that gives us

Ic_max = (Vcc - Vce_min) / (Rc + Re)

If the quiescent current is Ic_0, we then have

Ic_0 = Ic_max / 2 = (Vcc - Vce_min) / [2(Rc + Re)]

If we set Vce_min to 0 V to make life simple, we have the result I got before.

My guess -- and that's all it can be -- is that the authors made a simple math goof and didn't distribute the 2 in the denominator properly, and so ended up with 2Rc + Re by mistake. In this instance, the resulting error is small enough, about 5%, that it didn't raise any red flags. Of course, the mistake could just as easily have gone to make it 2Re + Rc, which would have totally messed up the results -- which might have been a good thing because the mistake would be more likely to have gotten caught.

But if they had presented their work properly -- and in doing so set a good example for how students should present their work and foster the habits of how engineers should present their work -- it would have been highly likely that someone working through the exercise would have caught the error and notified the authors/publishers within a few weeks of the first printing.

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
Actually, Q5 can go into saturation but Q6 won't. That's because if Q6 is in saturation, that would require Vce for Q5 to be negative.

But that's a pretty minor point and has little impact on the operation of the amplifier, since if ANY of the transistors go into saturation we are pretty much guaranteed that the amplifier as a whole is not behaving as it should.

In practice, we don't want to let Vout get too near Vcc or the minimum voltage, because in doing so we will likely have moved well outside the range of operation where we have good performance (e.g., low distortion). But those two theoretical operating points are useful because it allows us to park the quiescent operating point midway between them which gives us the best chance of obtaining the largest output voltage swing about that point that has acceptable performance. We probably won't have the actual optimum operating point, but we are probably close enough.

Another way to come up with the same result that I had before is to find the maximum possible current in Rc and set the quiescent current to half of that, which will park Vout in the middle of its output range.

Let's call the minimum collector-emitter voltage of Q6 Vce_min. Again assuming that Ic = Ie, that gives us

Ic_max = (Vcc - Vce_min) / (Rc + Re)

If the quiescent current is Ic_0, we then have

Ic_0 = Ic_max / 2 = (Vcc - Vce_min) / [2(Rc + Re)]

If we set Vce_min to 0 V to make life simple, we have the result I got before.

My guess -- and that's all it can be -- is that the authors made a simple math goof and didn't distribute the 2 in the denominator properly, and so ended up with 2Rc + Re by mistake. In this instance, the resulting error is small enough, about 5%, that it didn't raise any red flags. Of course, the mistake could just as easily have gone to make it 2Re + Rc, which would have totally messed up the results -- which might have been a good thing because the mistake would be more likely to have gotten caught.

But if they had presented their work properly -- and in doing so set a good example for how students should present their work and foster the habits of how engineers should present their work -- it would have been highly likely that someone working through the exercise would have caught the error and notified the authors/publishers within a few weeks of the first printing.
I think you're absolutely spot-on right, that the author made a goof in distributing the 2 across. Both your methods makes sense. I understand the the operating point is going to be in the active region which will occur somewhere roughly midway between saturation and cutoff. The cutoff extreme occur where we assumed Ic = 0, and the the other extreme (saturation), occured where we assumed Ic=max (and Vce = approx. 0. I'm catching your logic here.

I did some google searches for input resistance of Darlington, and I see that it involves the product of the two Betas. But what's different is that I don't see 2*re2 in any of the formulas for Darlington input resistance that I found online.

Also, why did they decide to multiply by 0.9? I don't see any intuitive reason for this.

#### WBahn

Joined Mar 31, 2012
30,236
Again, don't be afraid to knuckle down and do the analysis yourself. You seem to be falling into the trap of looking for canned results of other people's analysis.

One thing that this author seems to be doing is mixing the conventional notations for large-signal and small-signal parameter. Uppercase parameters, like R_in, are generally used for large-signal, while lowercase parameters, like r_in, refer to small-signal parameters.

You need to do the analysis twice -- once for large signal and once for small signal.

In large signal, apply a voltage, V_in, to the input and determine the current, I_in, the flows in it. In this case, you will get two components, a constant current (which is the current that flows when V_in = 0 V) and an additional component that flows that is proportional to V_in.

For small signal, you need to replace the transistors with their small-signal equivalents (you can use either the hybrid-pi or the tee model, whichever you like -- you might draw both and see which one looks like it will be easier to work with). Don't forget to zero out your DC sources and also to short low-frequency capacitors and open high-frequency capacitors -- this involves making some assumptions about the frequency of your small signal, and those assumptions should be stated.

So take your best shot at that and, if you get stuck, post your work and we'll see if we can get you unstuck.

#### WBahn

Joined Mar 31, 2012
30,236
As for the factor of 0.9 that seems to appear out of nowhere, my guess is that this is a rule-of-thumb factor.

If we have a quiescent current for Ic (the author claims it is 1.43 mA, but I think a better value would be 1.36 mA), the the voltage swing that would take you from the quiescent current to zero current would be Rc/Ic. But using this would have you operating right to the edge of cutoff and saturation. So, again my guess is that, the factor of 0.9 is there to establish a reasonable range of operation. Look back through the text and see if he introduces this notion at some point. It's not an unreasonable thing to do.

#### LvW

Joined Jun 13, 2013
1,765
Also, why did they decide to multiply by 0.9? I don't see any intuitive reason for this.
Because the result of Vout is a peak VOLTAGE (and the two last factors are the gain), the factor 0.9 must be the output peak VOLTAGE of the differential stage.

#### WBahn

Joined Mar 31, 2012
30,236
Because the result of Vout is a peak VOLTAGE (and the two last factors are the gain), the factor 0.9 must be the output peak VOLTAGE of the differential stage.
The last two factors are NOT a gain, they are a voltage. (0.00143 A)(4000 Ω) = 5.72 V.

That still leaves the question of why 0.9. Why not 0.5, or 1/sqrt(2), or 0.75? Where does the specific value 0.9 come from.

If it is the value needed to get 5.15 V deviation at the output, then where did the 5.15 V come from.

#### LvW

Joined Jun 13, 2013
1,765
The last two factors are NOT a gain, they are a voltage. (0.00143 A)(4000 Ω) = 5.72 V.
That still leaves the question of why 0.9. Why not 0.5, or 1/sqrt(2), or 0.75? Where does the specific value 0.9 come from.
If it is the value needed to get 5.15 V deviation at the output, then where did the 5.15 V come from.
* First line: Yes, you are right. The quantity "0.00143" is the current Ic=1.43mA.

#### WBahn

Joined Mar 31, 2012
30,236
Again, don't be afraid to knuckle down and do the analysis yourself. You seem to be falling into the trap of looking for canned results of other people's analysis.

One thing that this author seems to be doing is mixing the conventional notations for large-signal and small-signal parameter. Uppercase parameters, like R_in, are generally used for large-signal, while lowercase parameters, like r_in, refer to small-signal parameters.

You need to do the analysis twice -- once for large signal and once for small signal.

In large signal, apply a voltage, V_in, to the input and determine the current, I_in, the flows in it. In this case, you will get two components, a constant current (which is the current that flows when V_in = 0 V) and an additional component that flows that is proportional to V_in.

For small signal, you need to replace the transistors with their small-signal equivalents (you can use either the hybrid-pi or the tee model, whichever you like -- you might draw both and see which one looks like it will be easier to work with). Don't forget to zero out your DC sources and also to short low-frequency capacitors and open high-frequency capacitors -- this involves making some assumptions about the frequency of your small signal, and those assumptions should be stated.

So take your best shot at that and, if you get stuck, post your work and we'll see if we can get you unstuck.
@WARDEVIL_UFO: Have you had a chance to work through this?

Here's a hint, but it has a hole in it that you have to deal with by doing the analysis.

Consider the input resistance of a single BJT transistor. It's going to be ß·r_e, right. Do you agree that the effective ß of two transistors in a Darlington configuration is going to be the product of the two ßs? Now consider that the base current in the first transistor must pass not only through the small-signal emitter resistance of that transistor, but also through that of the second, so it's not unreasonable for the effective r_e of both of them to be related to the sum of the two. If they were the same, that would then be 2·r_e. But we know that they aren't the same, because r_e is related to the emitter current in the transistor and the emitter current in the first transistor differs from that in the second by the ß of the second transistor.

To see how this resolves, you need to do the analysis. Use the T-model for the transistors and ignore the output resistance (at least initially). You'll see where the factor of 2 comes from and what conditions need to hold for it to be valid.

#### LvW

Joined Jun 13, 2013
1,765
To see how this resolves, you need to do the analysis. Use the T-model for the transistors and ignore the output resistance (at least initially). You'll see where the factor of 2 comes from and what conditions need to hold for it to be valid.
In this context and for a better understanding, it may be helpful to point out the basic characteristics of the Darlington stage once again:
* High current gain (product of the individual "β-values")
* However, the total transconductance gm is reduced to about 50% of the second transistor.
* The total input resistance is doubled to the value of the first transistor.

Note: The very high current gain does not, of course, lead to a comparatively higher voltage gain (quite the opposite) - the Darlington stage is used primarily because of the greatly increased input resistance (compared to a single transistor with the same DC quiescent current Ic)

#### WARDEVIL_UFO

Joined Nov 16, 2010
41
Again, don't be afraid to knuckle down and do the analysis yourself. You seem to be falling into the trap of looking for canned results of other people's analysis.

One thing that this author seems to be doing is mixing the conventional notations for large-signal and small-signal parameter. Uppercase parameters, like R_in, are generally used for large-signal, while lowercase parameters, like r_in, refer to small-signal parameters.

You need to do the analysis twice -- once for large signal and once for small signal.

In large signal, apply a voltage, V_in, to the input and determine the current, I_in, the flows in it. In this case, you will get two components, a constant current (which is the current that flows when V_in = 0 V) and an additional component that flows that is proportional to V_in.

For small signal, you need to replace the transistors with their small-signal equivalents (you can use either the hybrid-pi or the tee model, whichever you like -- you might draw both and see which one looks like it will be easier to work with). Don't forget to zero out your DC sources and also to short low-frequency capacitors and open high-frequency capacitors -- this involves making some assumptions about the frequency of your small signal, and those assumptions should be stated.

So take your best shot at that and, if you get stuck, post your work and we'll see if we can get you unstuck.
I will attempt doing separate small signal analyses and Large Signal Model Analyses as you suggested. One thing I am worried about though, is my previous coursework from 2018 never covered Darlington Amplifiers. Allot of facts about Small signal and Large signal models have been coming back to me since my 2018 course, but I am still not as sharp with it as I once was. I will try drawing both of the models. I will withhold analyzing the drawing until I get some confirmation that my drawings are correct.

Throughout the course, I have tried doing the analysis on my own, but my answers rarely, if ever match up to the author's final results. I won't feel the confidence in my own approach until I get answers that match the text (assuming the author did a problem correctly of course). I am trying to follow the analysis of others so that I can develop some intuition on how to do it myself.

I also have limited intuition on if and when the author uses rules of thumb, unless explicitly stated within the text. The author seems to have more rules of thumb than I am aware of

The only 5 rules of thumb i know for BJT circuits:
1. The collector current will be approximately equal to the emitter current
2. The base current is ALMOST negligible compared to collector and emitter current.
3. The Collector-emitter junction at saturation is a short circuit
4. The collector-emitter junction when cutoff is an open circuit.
5. The base emitter junction has approximately 0.7V drop when BJT appreciably conducts. (active mode OR Saturation)

Beyond these rules of thumb, I don't know of any others. If the 0.9 thing is a rule of thumb, I never would have figured that out on my own.

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