I understand what common mode transients are. What I don't understand is why they are important at a deeper level.
This Ti app note says that:
Here is what I understand about CMT (particularly for transformer-based isolations):
This Ti app note says that:
What I don't get is why any of that would happen. Also are there more other/further consequences of insufficient CMTISome fault scenarios may include missing pulse, excessive propagation delay, high or low error or output latch, shown in Figure 3
Here is what I understand about CMT (particularly for transformer-based isolations):
There exists a capacitance across the isolation (interwinding capacitance in the case of transformers). When large dV/dt events (like switching a high-voltage MOSFET) happen on one side, a current is generated across the capacitor and that gets coupled to the other side through this capacitance.