# Coil driver - Adjacent power channels being partially energised unintentionally

#### LLofYorkshire

Joined Jan 15, 2020
21
Hi,
I have a problem on my 11 channel MOSFET based coil driver board. I have it programmed at the moment to cycle the output around the 11 channels then back to the start, with 3 channels active (50% duty) at any one time.

It works fine when I just have the LEDS switching on and off (no coil attached), but as soon as I connect a coil to one of the channels all other channels become partially active whenever that coil is powered. See Photo1 (normal behavior) and Photo2 (partially energised all channels)

I have my PWMs set to limit the current through the MOSFETs to about 2A. The PSU is set to 12V and has a current limiting function but I have it set unlimited for this test.

I don't have a scope, but I can see using my meter that on the channels that are partially high the gates of the MOSFETS are NOT being accidentally set high.
Voltage at the driven outputs are 12V as expected, and on the outputs that are unintentionally driven the voltage is 1.7V.
Any ideas please let me know.

OK behavior:

Schematic:

Close up on Channel layout:

Top Layer

Bottom Layer:

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#### KeithWalker

Joined Jul 10, 2017
1,299
What are the coils you are driving? Do you have a back EMF protection diode connected across each coil?
Regards,
Keith

#### cmartinez

Joined Jan 17, 2007
7,174
Hi,
I have a problem on my 11 channel MOSFET based coil driver board. I have it programmed at the moment to cycle the output around the 11 channels then back to the start, with 3 channels active (50% duty) at any one time.

It works fine when I just have the LEDS switching on and off (no coil attached), but as soon as I connect a coil to one of the channels all other channels become partially active whenever that coil is powered. See Photo1 (normal behavior) and Photo2 (partially energised all channels)

I have my PWMs set to limit the current through the MOSFETs to about 2A. The PSU is set to 12V and has a current limiting function but I have it set unlimited for this test.

I don't have a scope, but I can see using my meter that on the channels that are partially high the gates of the MOSFETS are NOT being accidentally set high.
Voltage at the driven outputs are 12V as expected, and on the outputs that are unintentionally driven the voltage is 1.7V.
Any ideas please let me know.

OK behavior:
View attachment 197916

View attachment 197915

Schematic:
View attachment 197920

Close up on Channel layout:
View attachment 197918

Top Layer
View attachment 197921

Bottom Layer:
View attachment 197922

Last edited:

#### Alec_t

Joined Sep 17, 2013
11,744
I may be interpreting your board layout incorrectly, but it looks like your FET source ground connections are daisy-chained rather than being in a star-ground configuration. Perhaps that could result in 'ground bounce' and consequent coupling between channels?

#### LLofYorkshire

Joined Jan 15, 2020
21
Thanks Guys. That gives me a couple of extra things to investigate. @Beau Schwabe The resistor is outside of the footprint of the copper pour, but the gate pin isn't so will look into that. That app you sent a link to is cool and wasn't aware of that parasitic capacitor effect. Borrowing a scope on Monday hopefully, and will just give the soldering of a resistor a go - nothing to lose.
I don't really understand properly what the ground plane would need to look like to achieve a star-ground, but now I know what to google I can learn about that, so thanks @Alec_t.
Hopefully have some further news by end of Monday
Have a great weekend.

#### cmartinez

Joined Jan 17, 2007
7,174
Question, what kind of power supply are you using for your circuit? And I mean for both the electronics and for powering the coils.

#### LLofYorkshire

Joined Jan 15, 2020
21
@cmartinez I'm using a bench-top supply for the 12V. Not very fancy - Maplins N93CX at moment, but have just borrowed something a bit higher power. The Sparkfun Thing (ESP32) is powered from the USB. The board as a 5-3.3V regulator on it. The grounds are tied on the custom PCB.

@Beau Schwabe to test for the parasitic capacitor effect I removed entirely R33 from the board. and grounded the Mosfet gate instead. It didn't stop the effect although it seems to have reduced the intensity f the LED on that channel. All of the gate resistors are directly
above the 12V "rail" so it does make sense that this could be the cause, but maybe it is only part of it.

I borrowed scope now so will see what I can find with that.
Cheers

#### LLofYorkshire

Joined Jan 15, 2020
21
I have attached 47K resistors as pull down resistors to all gates as per @Beau Schwabe suggestion. No change to behaviour.
Exploring a bit more with the scope but no solution yet, but I can see something going on unexpected, or possibly 2 different problems:

IMG_8629 shows a trace from the output pin of the MCU, for the channel that I disconnected from the MOSFET gate. It's 50% duty and all seems as expected. No 12V supply to the board, only the ESP32 powered.

IMG_8630 is a trace from the gate of a MOSFET, all channels except the disconnected one look the same as this. All settings on scope are unchanged. Again no 12V supply to the board, only the ESP32 powered.

IMG_8631 is a trace from the gate of the MOSFET on the channel that has the coil connected, and with the 12V supply powered on.

IMG_8632 is a trace from the gate of the MOSFET of an adjacent channel to the one powered with a coil attached (i.e. one of the channels that are activating when not commanded to do so). I left the scope settings unchanged as direct comparison, but the Amplitude measure shows that the MOSFET would almost certainly be partially on.

IMG_8629:

IMG_8630:

IMG_8631:

IMG_8632:

If this gives any clues - any pointers would be great, especially IMG_8630 as I have no idea what's going on there. Up to this point I thought all problems were coming from the parasitic effect from the 12V "high" current rail or the floating channels.

I looked into the Grounding. And I don't think it's daisy chained. @Alec_t . It would be just on the bottom layer, but the top layer connects through the Vias at the top area: