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In the following papers
I fail to understand why the potential at the gate of M3 (N3 respectively) becomes \(V_{DD}-V_{TH3}\)? Especially the term that the source of it 'floats to' I find most interesting?
Update:Could it be that because there is no current flowing through that FET,
\(V_{DS3} = V_{TH3}\)
?
- http://ijeit.com/vol%202/Issue%201/IJEIT1412201207_49.pdf
- http://www.fairchildsemi.com/an/AN/AN-140.pdf
I fail to understand why the potential at the gate of M3 (N3 respectively) becomes \(V_{DD}-V_{TH3}\)? Especially the term that the source of it 'floats to' I find most interesting?
Update:Could it be that because there is no current flowing through that FET,
\(V_{DS3} = V_{TH3}\)
?
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