Clock signal amplitude degradation when connecting to PIC port

Thread Starter

roxi60

Joined Sep 2, 2018
67
Hello.
I would like to enter with a clock signal in RB0 port of the PIC (see enclosed pdf).
My clock comes from a circuit with counters 74ls192 and at the end comes out from the 2 inverters.
When PIC is not connected, clock amplitude is about 4.1 V, when I connect PIC drops to 3 V and it is not detected.

How can I prevent the amplitude from dropping down (or even go to the required 5 V or an amplitude that is detected)?

Thank you.

clock-amplitude-degradation_roxi60.png

Mods Note:
Some members maybe have the safety concerned, so they don't like to open the .pdf file, and now it was copied and converted to the .png file.
 

Attachments

AlbertHall

Joined Jun 4, 2014
10,249
When PIC is not connected, clock amplitude is about 4.1 V, when I connect PIC drops to 3 V and it is not detected.
You have 4.1V labelled before the 100Ω resistor and 3V after that resistor.
What happens if you connect U1A/U1B output directly to the PIC without the resistors and Zener?
 

BobTPH

Joined Jun 5, 2013
2,506
No way a PIC input is pulling down the voltage that much. They draw at most 1uA (datashhet page 53)

Also, the threshold for reading a high is 2V unless you are using the external interrupt function.

So, I suspect it is NOT configured as an input.

Bob
 

Thread Starter

roxi60

Joined Sep 2, 2018
67
Max, Albert, Bob, many thanks for your kind replies.

I will try and study your suggestions/observations and I 'll let you know.

Thank you indeed.
 

Thread Starter

roxi60

Joined Sep 2, 2018
67
Thank you AnalogKid.

In the meantime I made some new checks and attempts with the original configuration of my first message (see enclosed revision, with measures on the oscilloscope) and the system now works properly, in spite of the lower voltage (so Bob was right 2 V are even enough, since it works with 3.5V).
RB0 is configured as input.
Don't understand why it didn't work before...

I'll also check your suggestions, to learn.
Max, can you sketch the connections of yours, 'cause I'm not sure I really understood well?
Thanks a lot to you all!
All the best.
 

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ericgibbs

Joined Jan 29, 2010
10,518
Morning roxi
I do not see the need for those two 7404 paralleled inverters.?
The 7400 should drive the PB0 pin OK.
If you are concerned about slow edges from the 7400, use a 7414 [Schottky] inverter, in place of the 7404's

E
 

LesJones

Joined Jan 8, 2017
2,687
The TRIS register is in bank 1. Have you remembered to select bank 1 before setting bits in the TRIS register ?
Note for others. The PIC seems to be a PIC16F84A from the schematics.

Les.
 

Thread Starter

roxi60

Joined Sep 2, 2018
67
Morning Eric, Les.

Eric: the two inverters are to increase the fan out (output current) in case to load more TTL IC (so it is written in the circuit instructions)

Les: program is not written by me, but I think yes, because it works properly with a clock in.
Yes it is 16F84A.

Many thanks for your kind replies.
 

LesJones

Joined Jan 8, 2017
2,687
The design of the output circuit of 74 series is designed to pull the output low. (To drive 74 series inputs which are multi emitter transistors which float high.) Try just adding a 1K pull up resistor to +5 volts. (Or change to using 4000 series logic.)

Les.
 

BobTPH

Joined Jun 5, 2013
2,506
So it is not the PIC input that is pulling the signal down, it is the network of R3, R4 and D2. Are you sure the values of these are as shown in the schematic? Is D2 perhaps a 3.6V Zener instead of 5.1? Or is R3 or R4 off? The values as shown should not pull it down much at all.

Agree with AK though, all of that is unnecessary since the PIC draws so little current.

Bob
 

Thread Starter

roxi60

Joined Sep 2, 2018
67
Thank you Max.
Bob: values are correct, on the body I read 5V1; also I guess it was chosen to guarantee 5 V supply on the PIC also in case of higher inputs. In any case I'll try direct connection (without).
Les: I appreciate your suggestion and will try it.

Thank you very much for your answers.
 

AnalogKid

Joined Aug 1, 2013
8,540
The schematic shows standard 7400 series TTL devices. TTL has a relatively weak output stage in the high (logic 1) state, with a high (for logic parts) output impedance. It is rated for a max output current of only 800 uA when sourcing current into a load. The schematic in post #9 indicates an output current of 1 mA in the high state. Even with two devices in parallel, the voltage drop you are seeing at that output current is completely normal.

Also, TTL isn't CMOS. It can't make a 5.0V output even with no load.

ak
 

BobTPH

Joined Jun 5, 2013
2,506
The schematic shows standard 7400 series TTL devices. TTL has a relatively weak output stage in the high (logic 1) state, with a high (for logic parts) output impedance. It is rated for a max output current of only 800 uA when sourcing current into a load. The schematic in post #9 indicates an output current of 1 mA in the high state. Even with two devices in parallel, the voltage drop you are seeing at that output current is completely normal.

Also, TTL isn't CMOS. It can't make a 5.0V output even with no load.

ak
How do you get 1mA? It looks to me like 2 gates driving a load of 10.1K, which, at 4V is 400uA, or 200 uA each.

Bob
 

ebp

Joined Feb 8, 2018
2,332
If you need good clean level shifting from TTL to CMOS, use something like a 74HCT00 or 74HCT132 (Schmitt trigger; useful if the input slew rate is low) instead of the TTL NAND gate. The power consumption will be greatly reduced and the output will swing from nearly rail to rail. If higher speed is required, use ACT parts instead of HCT.
AC is available only in surface mount and most manufacturers have quit making HC in through-hole packages. Very tiny SM packages with 1 gate or 2 inverters are available in similar CMOS logic families.

In the existing circuit the zener diode is probably responsible for most of the voltage drop across the 100 ohm resistor. Zeners in that voltage range begin to conduct significant current well below their nominal voltage and are generally poor for protecting inputs (and completely unnecessary in this case).
 
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