When power is initially applied it may go through a pulse sequence before stopping with the Inh signal high.
Is that a problem?
The 555 is enabled when the RST input is open.

I don't like the CD4017B IEC symbol...but that's just me.

Which pin is the clock pin (pin 14)?
Pin 13, INH, has to be low for the CD4017 to advance.

 

When power is initially applied it may go through a pulse sequence before stopping with the Inh signal high.
Is that a problem?

The inh is pulled to VDD(?)
I think the 555 will output one pulse at startup.

 

Which pin is the clock pin (pin 14)?

Yes, pin 14 is the clock input, but I'm using the INH input as the clock, since I need the 4017 to advance on the fall of the clock input.

Pin 13, INH, has to be low for the CD4017 to advance.

I'm using pin 13 as the clock input.
The INH input is simply the inverse polarity of the CLK input.

I think the 555 will output one pulse at startup.

How do you figure?
The 555 will output clock pulses until the Q3 output of the CD4017 goes high.
So the number of pulses will depend upon what state (likely random) the CD4017 assumes when power is applied.

 

Yes, pin 14 is the clock input, but I'm using the INH input as the clock, since I need the 4017 to advance on the fall of the clock input.

So you've connected the 555 output to the INH pin?

 

Yes, pin 14 is the clock input, but I'm using the INH input as the clock, since I need the 4017 to advance on the fall of the clock input.

I've redrawn and simulated your circuit so I could better understand. I used a mosfet instead of BJT (the results are the same).

 

I was working on this while eetech posted. It is a bit off topic, but ...

As eetech shows in #25, 555 circuits become easier to connect and dissect when the device pins are moved around. I never have modified anything in LTS successfully, but that's probably more about me than about LTS. His sch has a clear left-to-right signal flow with reduced net crossovers. To expand on that, here are three versions of the #9 oscillator circuit.

A - Re-arranged and re-drawn to bring out the Reset net for direct connection to Q1. This uses an already existing decal that was close enough to start with.

B - Clarified even more by moving the Reset pin. This uses a new decal created for this post.

C - Similar to B, but with the alternate timing component connections for a near 50/50 output duty cycle with one fewer component.

All three include the R2-R3-D1 components to correct the output pulse width in the first half-cycle. Without them, the first 555 high output state will be approx. 40% longer than the succeeding ones. This is a common aspect of many R-C oscillator circuits. The circuit powers up with 0 V across timing capacitor C1, but the minimum voltage for all succeeding cycles is Vdd/3, approx. 3 V in your circuit. For the first half-cycle, the cap has to charge up from 0 V to 6 V, while for the remaining cycles it charges up from 3 V to 6 V. The voltage across the capacitor increases inverse-exponentially, not linearly, which is why a 2:1 difference in voltage span does not produce a 2:1 change in timing.

My two circuits have the same "feature", and the same addition (with one resistor value change) will correct it. If the longer first relay pulse is not an issue, these three components can be deleted.

ak

 

555 circuits become easier to connect and dissect when the device pins are moved around. His sch has a clear left-to-right signal flow with reduced net crossovers.

Sorry if my 555 pin model bothers you, but its the one I have in LTspice, which shows the DIP pin locations, and I'm too lazy to modify the model.

 

Nice to see that the wizard is slowing down to my speed.

ak

 

Nice to see that the wizard is slowing down to my speed.

I just read a saying I can relate to:

Some days I wake up with nothing to do -- and it takes me all day to do it.

 

I was working on this while eetech posted. It is a bit off topic, but ...

As eetech shows in #25, 555 circuits become easier to connect and dissect when the device pins are moved around. I never have modified anything in LTS successfully, but that's probably more about me than about LTS. His sch has a clear left-to-right signal flow with reduced net crossovers. To expand on that, here are three versions of the #9 oscillator circuit.

A - Re-arranged and re-drawn to bring out the Reset net for direct connection to Q1. This uses an already existing decal that was close enough to start with.

B - Clarified even more by moving the Reset pin. This uses a new decal created for this post.

C - Similar to B, but with the alternate timing component connections for a near 50/50 output duty cycle with one fewer component.

All three include the R2-R3-D1 components to correct the output pulse width in the first half-cycle. Without them, the first 555 high output state will be approx. 40% longer than the succeeding ones. This is a common aspect of many R-C oscillator circuits. The circuit powers up with 0 V across timing capacitor C1, but the minimum voltage for all succeeding cycles is Vdd/3, approx. 3 V in your circuit. For the first half-cycle, the cap has to charge up from 0 V to 6 V, while for the remaining cycles it charges up from 3 V to 6 V. The voltage across the capacitor increases inverse-exponentially, not linearly, which is why a 2:1 difference in voltage span does not produce a 2:1 change in timing.

My two circuits have the same "feature", and the same addition (with one resistor value change) will correct it. If the longer first relay pulse is not an issue, these three components can be deleted.

ak
View attachment 329489

Im sorry, I do not understand these 3 circuits, Im just not that bright! As well, is this in addition to the initial circuit that is connected to the 2x 4017s to be triggered when 2 leds are lit??

 

I've redrawn and simulated your circuit so I could better understand. I used a mosfet instead of BJT (the results are the same).

View attachment 329487

View attachment 329488

Is this circuit "safe" to use as it stands, as I understand this one better.

how are these circuits interfaced with the initial circuit in post #1. I still require this circuit to act like this circuit in Post#1, initiating only when specific leds on 2 individual 4017s are triggered. I would like to thank everyone involved in the amazing work so far.

Is this circuit triggered by the circuit is post#1?

 

I still require this circuit to act like this circuit in Post#1, initiating only when specific leds on 2 individual 4017s are triggered.

My 555/4017 circuit has two AND inputs which both must be high to trigger the circuit.
Is that what you want?
If not, exactly what LED conditions do you want for the circuit generate the pulses?

 

My 555/4017 circuit has two AND inputs which both must be high to trigger the circuit.
Is that what you want?
If not, exactly what LED conditions do you want for the circuit generate the pulses?

I do apologize, I now see that this has been included, thank you very much for that

 

My 555/4017 circuit has two AND inputs which both must be high to trigger the circuit.
Is that what you want?
If not, exactly what LED conditions do you want for the circuit generate the pulses?

Are the triggers D2 nd D3?, Thanks

 

Are the triggers D2 nd D3?, Thanks

Yes.

 

Yes.

Thank you

 

I don't like the CD4017B IEC symbol...but that's just me.

You are not alone. I don’t like them either. Supposedly they are more intuitive and provide all the pertinent pin information, but still…. I am an old fart and I don’t like them.

 

Why are there circles on certain pins of the 555??

 

Why are there circles on certain pins of the 555??

A circle indicates that input is active low, thus, for example, the 555 is reset when the RST input is connected to ground.

 

A circle indicates that input is active low, thus, for example, the 555 is reset when the RST input is connected to ground.

I must apologize, but I still do not understand D2 and D3 in your schematic. the 2 diodes as far as input are shorted together, should they not be separate, each wired to a led output of 1 of the 2 4017s. Im sorry, I am having problems un understanding it