Do u think the circuit is correct.See from the circuit if the complimented output of 1st f//f is 1 and second normal output is 0.Then whats the one of the input of and gate.The two outputs wires are merged is that correct?

 

Where did you get that circuit?

 

The first /Q will be conflict with the second Q when they are on the different level as one is Low and another is High.

 

Hello Bhuvanesh

And yes, where did you get that circuit ?

If (A 'Q)=1 and (Q B)=0 we will have 1/2. . . No sorry it's just a joke.

What we would get is an undefined state.
but. . . if B can sink more current than A will have a 0.
Etc.

That kind of connection is unusual because most of the time we will have a undefined state. also one of the two flip-flops may be damaged.

Remove that conflicting line. Then try to answer the question that is at the bottom of your picture. The ripple counter shown in fig works as a: .

 

With respect to the circuit as drawn, the answer to the question is ... a poorly designed circuit.

I'm still interested in the source ... but I will offer this observation, if the source is the OP, the problem has been pointed out concerning the AND gate. If it's from the instructor, that's a different story. It is possible the student failed to copy the diagram correctly, thereby the student needs to exercise due diligence when taking notes.

My crystal ball is in the wizards' shop being updated with new cloudware, so further guessing is futile.

 

answer is mod 5 down counter.

 

The second Q should be cut off from the first /Q.

For a practical logic IC as 74LS76 or 74HC76, you need to connecting the output of NAND gate to the clear or reset pins, and connecting the set or preset pins to +V.