Always taught never to have pull-down resistors. Recipe for noise problems.

 

That's a very useful model.
If you could post the model and symbol files, I'd appreciate it.

Sure...I need to clean it up a little...then I'll post..

 

Always taught never to have pull-down resistors. Recipe for noise problems.

Certainly that is possible in ANALOG systems, and in poorly laid out/assembled digital systems. Properly connected pull-down resistors have never been a problem for me, except when I used too high a value of the resistor. I learned from that.

 

For CMOS inputs without Schmidt triggers, a slow input with not trigger on either edge as stated several times here. What happens, because CMOS logic are push/pull devices (the "complementary" part) and their gain is low for the older CD series, so the clock input amplifies the slow input (the time constant you chose is 220 sec!) (also the inputs have some capacitance), as the slow input rises, the output of the logic level clock input can switch MULTIPLE times on a single slow edge which can toggle the output several times! Check it using a fast scope input. Also, when this happens, you many need a bulk (bigger) power bypass capacitor, since the slow rising input's N and P channel MOSFETs can short out the power supply, which can also add bounce. I played with these back in 1975 where I used "real" RCA chips (RCA was the creator of CD series CMOS). Look at the chip's schematic from an old datasheet that literally shows the raw internal circuit. Most datasheets now only show a logical equivalent which is worthless for this kind of analysis. Even if you got your knowledge from college, they really don't go into the details of this, which some would say is a lost art, but it's worse, it's neglect.

 

(the time constant you chose is 220 sec!)

The time-constant in my circuit is 470ms.

so the clock input amplifies the slow input

Which clock input?
What circuit are you referring to?

 

That's a very useful model.
If you could post the model and symbol files, I'd appreciate it.

Per your request. Here is switch with bounce model.
I've included a test circuit, SPSTNO and SPSTNC symbols and model file.
I did not include the CD4000_v.lib file.

Here's a demo of the included Test circuit.

 

For CMOS inputs without Schmidt triggers, a slow input with not trigger on either edge as stated several times here. What happens, because CMOS logic are push/pull devices (the "complementary" part) and their gain is low for the older CD series, so the clock input amplifies the slow input (the time constant you chose is 220 sec!) (also the inputs have some capacitance), as the slow input rises, the output of the logic level clock input can switch MULTIPLE times on a single slow edge which can toggle the output several times! Check it using a fast scope input. Also, when this happens, you many need a bulk (bigger) power bypass capacitor, since the slow rising input's N and P channel MOSFETs can short out the power supply, which can also add bounce. I played with these back in 1975 where I used "real" RCA chips (RCA was the creator of CD series CMOS). Look at the chip's schematic from an old datasheet that literally shows the raw internal circuit. Most datasheets now only show a logical equivalent which is worthless for this kind of analysis. Even if you got your knowledge from college, they really don't go into the details of this, which some would say is a lost art, but it's worse, it's neglect.

Interesting.
I’ve heard of gate lengths of 7, 9, or 10 microns for CD4000B devices.
can you share what the real gate length is?