Hello again,

In the past when I had used flip flops and counters I always used a SPDT switch instead of a SPST. That way you can control the pulse every time with no miss. In order for the state to change, the SPDT switch MUST return to it's home position. When used with a RS latch that makes a perfect pulse out which can be used successfully as a clock. This kind of front end requires either another flip flop or two inverters and possibly two resistors. If interested, I'll show the circuits.

Also, has anyone tried to DELAY the Qnot output to the D input? If that signal was delayed I think it would take two pushes to toggle the flip flop. That's if that kind of operation is ok to do. While the delay is timing out, the clock would not be able to change the state of the flip flop again (possibly). Only after the delay and the button is pressed again the clock would toggle the FF but then there would be another delay which would again prevent two clocks from flip-flopping the flip flop (ha ha).

 

In the past when I had used flip flops and counters I always used a SPDT switch instead of a SPST. That way you can control the pulse every time with no miss. In order for the state to change, the SPDT switch MUST return to it's home position. When used with a RS latch that makes a perfect pulse out which can be used successfully as a clock. This kind of front end requires either another flip flop or two inverters and possibly two resistors. If interested, I'll show the circuits.

I was going to mention that, but there are so few SPDT pushbuttons I thought it wasn't worth it. You could use the other half of the 4013 as a S-R latch.

Also, has anyone tried to DELAY the Qnot output to the D input?

@crutschow mentioned it, but the problem is that the slow edge on CLK causes it to toggle on both edges, or multiple times, so that doesn't help. The only fix is to tidy up the input waveform to give it a fast rising edge.

 

I was going to mention that, but there are so few SPDT pushbuttons I thought it wasn't worth it. You could use the other half of the 4013 as a S-R latch.

@crutschow mentioned it, but the problem is that the slow edge on CLK causes it to toggle on both edges, or multiple times, so that doesn't help. The only fix is to tidy up the input waveform to give it a fast rising edge.

Hi,

What post was that I'll check it out ?

It seems that the only way the FF can flip or flop is if the D input changes once it flips which gets the FF ready for the next clock pulse. If we do not let the D input change, no matter how many clocks we preset to the CLK input the FF can not flip a second time.
So say the Qnot is 0 then the D input is zero. On the next CLK pulse Qnot will change to 1 and Q will change to 0, but that can only happen when the D input is at 0. If we delayed that D signal, then it would not have been 0 yet so the next CLK would not be able to flip the state, if I understand this right. Let me make a table or two...

With no delay:
Q=1, Qn=0, D=0, CLK goes 0 to 1, then Qn=1, Q=0, D=1, then
CLK goes 1 to 0 then 0 to 1 again, the states change. Normal operation.
Now with delay:
Q=1, Qn=0, D=0, CLK goes 0 to 1, then Qn=1, Q=0, D still at 0 for the delay time, then while still at zero then
CLK goes 1 to 0 then 0 to 1 again, the states do not change yet because D is still at 0.
Now after the delay times out, D follows Qn and so goes to 1, and now it's ready for the next clock. Then later
CLK goes 1 to 0 then 0 to 1 again, now the states change again.

So it 'seems' that the delay will act as a switch debouncer time delay period. It would only work though if the switch was not held down for too long. It seems that way anyway. If the delay is long enough it might work if the user knew that they could not hold the push button switch down for too long. Alternately, perhaps a gate (like NAND) in combination with this so that the delay can not start to time out until the switch is released.
Note I have not tried this or simulated this yet.

 

I was going to mention that, but there are so few SPDT pushbuttons I thought it wasn't worth it. You could use the other half of the 4013 as a S-R latch.

Yes, I know that there are few SPDT tactile switches. There are some panel mount pushbuttons.
If TS indicates the application I can search for one.

 

This should work.

 

This should work.

It might, but I don't see why it should.
You have a time constant R5-C7 of 22uS. Rise time will be about 3 times that, but TI's 4013 datasheet specifies maximum rise AND FALL times of 10us for the clock input.

 

It might, but I don't see why it should.
You have a time constant R5-C7 of 22uS. Rise time will be about 3 times that, but TI's 4013 datasheet specifies maximum rise AND FALL times of 10us for the clock input.

Only the differentiator rise time is seen by the clock input. But C1 could be smaller.
I have plenty of TI CD4013B, I test on breadboard.

Edit: Might be more reliable to use set input instead of clock input (pull this low)

 

Below is the LTspice sim of the CD4013 FF with an RC delay in the D feedback path:

Its output (yellow trace) ignores the simulated bounce from the PB (green trace) due to the RC delay in the D input signal (blue trace).

Since there is now no debounce circuit required on the PB output, there is not an issue with a slow clock rise-time.

One possible problem with this circuit is that it does not ignore any bounce when the PB is released, but that doesn't often occur.

 

Here's my take on the circuit. It works as follows:
Assume Q is Low and we clock the FF. Q goes High, and the capacitor connected to it drives Preset pin 6 High, holding the FF in the set state until the 1M resistor discharges it to a low enough level that the preset is de-asserted. All this time the clock input is ignored. Eventually the Clock is enabled again and on the next push, the /Q goes High, and its capacitor combo does the same as before.
I found that I could pump the push button 5 or 6 times quickly before it registered the toggle pulse to switch!



I used Schottky diodes because they were handy. Probably the diode on the clock isn't truly necessary given the small capacitor, but I'd not want to use the two 1uF caps without them. Oh, this was using a TI chip, by the way.

 

Here's a circuit that ignores any switch bounce on both press and release (sim below):
It has a fast rise time (<1µs) for the clock but ignores any bounce after that.
It also is insensitive to the length of the bounce period.

Edit: This circuit is likely problematic because the slow fall-time could also cause false toggling.

 

It also needs a fast fall time, otherwise it will clock on both edges.

 

Only the differentiator rise time is seen by the clock input. But C1 could be smaller.
I have plenty of TI CD4013B, I test on breadboard.

Unfortunately not - the differentiator can't make the rise-time any quicker.
Not quite sure how the SET would help. What would reset it?

 

And you have observed this to be true?

Yes (though it was years ago).
It was used to synchronise logic signals to the mains, prior to driving triacs. It was on a 9V supply tied to mains live.
Clock was connected to neutral via a 1M resistor (leaving the protection diodes to clamp the voltage)
Texas and SGS-Thomson devices clocked on both edges. Philips and Toshiba devices behaved correctly.

Main suspect at the time was the lack of voltage clamp diodes, but adding Schottkies made no difference.

 

Sorry, I deleted my post when I realized what you said is likely true.
So my circuit in post #50 won't work.

 

Sorry, I deleted my post when I realized what you said is likely true.

Valid question, nonetheless.
The other main suspect was the supply, which had about 1V of 50Hz ripple.
That proved to be a red herring as well.

 

So here's my take on using 1/2 of the CD4013 IC as a simple debounce circuit with fast rise/fall output times to clock the toggle FF:
R2C2 provides a delay so that bounce on both the closing and opening of the PB switch (blue trace) is suppressed.
The circuit uses the CD4013 characteristic that when both PRE and CLR are high the Q output is high.

Edit: Added hysteresis to the debounce circuit to make it a Schmitt-trigger and minimize the chance of U1a oscillating during the slow fall time of the Pre signal.

 

Unfortunately not - the differentiator can't make the rise-time any quicker.
View attachment 330348View attachment 330349Not quite sure how the SET would help. What would reset it?

Move the PB input connection from the clock to the set pin along with some value adjustments.
I don't see the same rise time limitation for the set/reset pins as the clock on the TI datasheet.
Below, the reset function overrides the set function once the FF is set.

 

This version has corrected pin numbers and I also swapped C2/R2.
I tested it on the bench using a supply of 3-15v and an LED for the load.
The flip flop is a TI CD4013B. I pressed the button as fast as I could. It toggled U1B correctly and I couldn't make it fail.

 

This version has corrected pin numbers and I also swapped C2/R2.
I tested it on the bench using a supply of 3-15v and an LED for the load.
The flip flop is a TI CD4013B. I pressed the button as fast as I could. It toggled U1B correctly and I couldn't make it fail.

View attachment 330442

And look how complicated is has become, compared to the circuit in post #10!

 

And look how complicated is has become, compared to the circuit in post #10!

True.
My circuit is post #56 is also simple, requiring only 3 passive parts plus one of the two FFs in the CD4013 package, and thus doesn't necessarily need another gate package.