Capacitor in series with SGMII/ high speed designs

Thread Starter

selva97

Joined Nov 30, 2020
21
Hi,
Why we are using capacitor in series with SGMII or high speed designs, If it is for removing DC, then why are we not using it in other signal lines like DDR. I have seen many documents but no clear and easy explanation reg it, so anyone explain it in easy way?

Thanks
 

Papabravo

Joined Feb 24, 2006
17,316
Thanks, but still have many doubts reg it, why we are not using it in other signal lines?
This is only a guess, but AC coupling of a signal onto transmission lines has a couple of benefits:
  1. Reduced DC power consumption in the termination network
  2. Elimination of common mode ground differences
  3. At 1GHz. the impedance of a 0.01uFd capacitor is about 16 milliohms, which means a very small degradation of the signal quality.
  4. The effect is identical on both elements of the differential pair.
 

Thread Starter

selva97

Joined Nov 30, 2020
21
thanks, when taking about ground i came to know that, though i have same IC operating at same voltage. But some searches says that they dont have same ground, like absolute zero potential at ground. is it true and how it affects the system
 

Papabravo

Joined Feb 24, 2006
17,316
thanks, when taking about ground i came to know that, though i have same IC operating at same voltage. But some searches says that they dont have same ground, like absolute zero potential at ground. is it true and how it affects the system
Imagine a long cable of say 100 meters or so and you have a GROUND potential difference of 10 Volts. How is a transceiver that depends on the ground difference being less than 5 volts going to deal with the problem. You may think that two chips have the same ground, but long cables can upset that assumption. Your original question did not specify any particular set of geometric constraints. You asked an open ended question with no constraints. Why do you care about whether the signals are AC coupled or not?
 

Thread Starter

selva97

Joined Nov 30, 2020
21
ok, i didnt mention previously, after searching in internet, i found like the ground potential of two IC may varies, so capacitor is used as level shifter in some case, but still im not 100% sure why we are using it and where we need to use it.
 

Papabravo

Joined Feb 24, 2006
17,316
ok, i didnt mention previously, after searching in internet, i found like the ground potential of two IC may varies, so capacitor is used as level shifter in some case, but still im not 100% sure why we are using it and where we need to use it.
The purpose of the capacitor is NOT to serve as a level shifter. This is a true differential signal where the absolute signal levels DO NOT MATTER. In differential signaling you want to do the same thing to both conductors of a pair and you want to remove the effect of ground differences so the differential transmitter and receiver can do their jobs. The technical details are beyond the scope of a forum post and you might benefit from a general investigation of the benefits of differential signaling.
 

Deleted member 115935

Joined Dec 31, 1969
0
Hi,
Why we are using capacitor in series with SGMII or high speed designs, If it is for removing DC, then why are we not using it in other signal lines like DDR. I have seen many documents but no clear and easy explanation reg it, so anyone explain it in easy way?

Thanks
A good question,
just get this out there first,
its not mandatory to use AC coupling high speed signals,
its just normal,

DDR, is typically a single ended signal, over a short length ,
Its a logic effectively derived from the classic TTL signal states.
A 0 is a voltage below a threshold, a 1 is a voltage above a threshold.
DDR , just means that data changes on the falling and rising edge of the clock,

The DDR signal typically has a DC component, i.e. a string of '1' is possible,
If this was AC coupled, the DC would be removed, and the signal would fail.

DDR, is typically also data and clock,
data is on sperate wires to the clock,
and you can have multiple data lines,
as the alignment of the clock to the data is critical,
making the tracks longer adds more chance for the data to be out of sync

If the length of the DDR is increased, the all the problems increase also,

SGIIM , is an encoded stream ,
a serial link, think of it as a very fast RS232 link,
If the stream is as you say AC coupled,
that means there is no DC on the link,
the advantage of AC coupling, and differential, is that the receiver and transmiter are not reference to the ground,
First up, any noise on the ground is not a problem,
secondly, when you make a fast receiver, you design it to work around a bias voltage ,
now if the receiver provides that voltage itself, and the transmitter is DC coupled to the receiver,
the DC can be upset. So if the encoding is such that it can be AC coupled, then there is no chance of upseting the bias,
 

Thread Starter

selva97

Joined Nov 30, 2020
21
First of all , thank a lot. Why it is specific for encoded system, still encoded too has o and 1 like other signals.
 
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