A gated SR latch has unpredictable behavior if the S and R inputs are both equal to 1 when the Clk changes to 0. One way to solve the problem is to create a set-dominant gated SR latch in which the condition S = R = 1 causes the latch to be set to 1. Design a set-dominant gated SR latch and show the circuit.

Okay I've provided my attempt in the figure attached as well as the solution given in another figure.

I think there is a problem with the solution given. They state "Design a set-dominant gated SR latch", the latch they've provided in the solution is not a gated SR latch.

Is the solution incorrect?

 

I 'm not into latches and FFs so deep, but you could say that there's a controlling gate before the latch, at the solution circuit. It's a matter of definition I guess.

Your attempt is superior to the one proposed, as it incorporates both security checks.

 

They are both correct. But the one with the clock is far better. I would advise you to use 4 nand gates

 

Your solution is incorrect. The correct solution can be found @
http://electronics.stackexchange.co...ow-do-i-make-it-a-set-dominant-gated-sr-latch