A gated SR latch has unpredictable behavior if the S and R inputs are both equal to 1 when the Clk changes to 0. One way to solve the problem is to create a set-dominant gated SR latch in which the condition S = R = 1 causes the latch to be set to 1. Design a set-dominant gated SR latch and show the circuit.
Okay I've provided my attempt in the figure attached as well as the solution given in another figure.
I think there is a problem with the solution given. They state "Design a set-dominant gated SR latch", the latch they've provided in the solution is not a gated SR latch.
Is the solution incorrect?
Okay I've provided my attempt in the figure attached as well as the solution given in another figure.
I think there is a problem with the solution given. They state "Design a set-dominant gated SR latch", the latch they've provided in the solution is not a gated SR latch.
Is the solution incorrect?
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