How do i make this circuit with logism?
i have to build it only with OR,AND,NOT,XOR,XNOR,D-flipflops
part 1. making 4 bit register using flip flops: circuit should perform read and write in one clock cycle:
when enabled: read_write = 1, En = 1,
and data will be saved in flip-flops.
value appear in Nib_Out within one clock cycle
if En = 0, no write operation ==> last value of nibble should be represented as Nib_Out
when read_write = 0, value should be observed on the Nib_out regardless of what En is.
part 2. building 16-nibble RAM:
using the register from part 1, add additional circuit to implement this...
1. circuit perform read and write in one clock cycle: to read from RAM (read_write = 0), with next clock tick, value of nibble that address bits indicate should be in Ram_Out
2. RAM circuit should read 4-bit piece of data as input and set this as value of nibble
if Data = 1000, Address = 0011, in the next clock cycle the value of 4th nibble should become 1000 and value should be displayed on output
3. entire circuit should have just one single clock signal
i have to build it only with OR,AND,NOT,XOR,XNOR,D-flipflops
part 1. making 4 bit register using flip flops: circuit should perform read and write in one clock cycle:
when enabled: read_write = 1, En = 1,
and data will be saved in flip-flops.
value appear in Nib_Out within one clock cycle
if En = 0, no write operation ==> last value of nibble should be represented as Nib_Out
when read_write = 0, value should be observed on the Nib_out regardless of what En is.
part 2. building 16-nibble RAM:
using the register from part 1, add additional circuit to implement this...
1. circuit perform read and write in one clock cycle: to read from RAM (read_write = 0), with next clock tick, value of nibble that address bits indicate should be in Ram_Out
2. RAM circuit should read 4-bit piece of data as input and set this as value of nibble
if Data = 1000, Address = 0011, in the next clock cycle the value of 4th nibble should become 1000 and value should be displayed on output
3. entire circuit should have just one single clock signal