Good morning/ Evening. I am trying to design a buck converter. My requirments is that the closed loop output impedance is less than 0.2 across all frequencies till 20kHz.
So I designed everything on paper, just couldnt asses the closed loop output impedance. Trying now to simulate the whole converter with the feedback loop to assess my design. I added a PID and chose a phase margin of 45 degree, a gain of about 23 at10kHz which is the closed loop crossover frequency. Also designed an inverted zero at 1kHz.
The output of the pid is as in the ss downards with a gain of about 29db and a phase margin of 40degree which is close to what I designed.
My input voltage is 100, the output voltage is also 100. It;s like there is no switching taking place.
I looked at the time domain signal coming of the PID and I found that the error is very much greater than one which makes the duty cycle equal to one.
I would really appreciate any help. I have been stuck at this for three weeks now, I wish to move onto practical stuff but I am just unable since my simulations are shit to say the least lol.
So I designed everything on paper, just couldnt asses the closed loop output impedance. Trying now to simulate the whole converter with the feedback loop to assess my design. I added a PID and chose a phase margin of 45 degree, a gain of about 23 at10kHz which is the closed loop crossover frequency. Also designed an inverted zero at 1kHz.
The output of the pid is as in the ss downards with a gain of about 29db and a phase margin of 40degree which is close to what I designed.
My input voltage is 100, the output voltage is also 100. It;s like there is no switching taking place.
I looked at the time domain signal coming of the PID and I found that the error is very much greater than one which makes the duty cycle equal to one.
I would really appreciate any help. I have been stuck at this for three weeks now, I wish to move onto practical stuff but I am just unable since my simulations are shit to say the least lol.
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